CN-114255817-B - Pattern generation for multi-channel memory arrays

Abstract

The application relates to pattern generation for a multi-channel memory array. A device may include a memory array and circuitry for testing the memory array. The memory array may include a first set of memory cells coupled with a first channel and a second set of memory cells coupled with a second channel. The circuit may be coupled with the memory array and may include a pattern generator and an output response analyzer. The pattern generator may be configured to selectively output a single pattern when operating in a single pattern mode or to selectively output a plurality of patterns when operating in a multi-pattern mode. The output response analyzer is configured to determine whether the memory array includes one or more errors based at least in part on a pattern output by the pattern generator.

Inventors

• Xin Shangxun

Assignees

• 美光科技公司

Dates

Publication Date

20260512

Application Date

20210922

Priority Date

20200923

Claims (19)

1. 1. An apparatus, comprising: A memory array comprising a first set of memory cells coupled with a first channel and a second set of memory cells coupled with a second channel, and Circuitry coupled with the memory array and comprising: A pattern generator configured to selectively output a single pattern in response to operating in a single pattern mode of a test program, and to selectively output a plurality of patterns in response to operating in a multi-pattern mode of the test program; An output control configured to communicate a first pattern of the plurality of patterns to the first channel and a second pattern of the plurality of patterns to the second channel in parallel in response to the pattern generator operating in the multi-pattern mode of the test program, and communicate the single pattern to the first channel and the second channel when the pattern generator operates in the single-pattern mode of the test program, an An output response analyzer configured to determine whether the memory array includes one or more errors based at least in part on a pattern output by the pattern generator.
2. 2. The apparatus of claim 1, wherein the output control comprises a selector coupled with the second channel of the memory array and configured to selectively output the first pattern from the pattern generator to the second channel or to selectively output the second pattern from the pattern generator to the second channel based at least in part on whether the pattern generator is operating in the single pattern mode or the multi-pattern mode.
3. 3. The apparatus of claim 1, wherein the circuit further comprises a controller configured to cause the circuit to perform the test procedure.
4. 4. The apparatus of claim 3, wherein the controller is further configured to cause the pattern generator to operate in the single pattern mode or the multi-pattern mode.
5. 5. The apparatus of claim 3, wherein the circuit further comprises: a sequencer configured to receive one or more commands from the controller and generate one or more signals to initiate the pattern generator.
6. 6. The apparatus of claim 1, further comprising: a test collar configured to selectively couple the memory array with the circuit or with a host device.
7. 7. The apparatus of claim 1, further comprising: a high bandwidth memory interface coupled with the memory array and a host device.
8. 8. The apparatus of claim 1, wherein the circuit is located on a first die that is different from a second die of the memory array that includes memory cells.
9. 9. A method, comprising: identifying whether a pattern generator of a circuit coupled to the memory array operates in a single pattern mode or a multiple pattern mode; dividing a data set for testing the memory array into a first portion and a second portion based at least in part on identifying that the pattern generator is operating in the multi-pattern mode; transmitting the first portion of the data set to a first channel of the memory array and the second portion of the data set to a second channel of the memory array in parallel based at least in part on dividing the data set, and Determining whether the memory array includes one or more errors based at least in part on transmitting the first portion of the data set to the first channel and transmitting the second portion of the data set to the second channel.
10. 10. The method as recited in claim 9, further comprising: Identifying an indicator associated with the dataset, wherein identifying whether the pattern generator operates in the single pattern mode or the multi-pattern mode is based at least in part on identifying the indicator.
11. 11. The method as recited in claim 10, further comprising: A first number of instructions in the first portion of the dataset and a second number of instructions in the second portion of the dataset are identified based at least in part on the indicator, wherein partitioning the dataset is based at least in part on identifying the first number of instructions and the second number of instructions.
12. 12. The method as recited in claim 10, further comprising: A first direction of an instruction to increment the first portion of the data set and a second direction of an instruction to increment the second portion of the data set are identified based at least in part on the indicator, wherein transmitting the first portion of the data set and the second portion of the data set is based at least in part on identifying the first direction and the second direction.
13. 13. The method as recited in claim 9, further comprising: Generating a signal configured such that a selector transmits the first portion of the data set to the second channel or transmits the second portion of the data set to the second channel based at least in part on identifying whether the pattern generator is operating in the single pattern mode or the multi-pattern mode, wherein transmitting the first portion of the data set and the second portion of the data set is based at least in part on generating the signal.
14. 14. The method as recited in claim 9, further comprising: retrieving the data set from a memory, wherein identifying whether the pattern generator operates in the single pattern mode or the multi-pattern mode is based at least in part on retrieving the data set from the memory.
15. 15. The method as recited in claim 9, further comprising: Identifying that the pattern generator is operating in the single pattern mode; Transmitting a second data set to the first channel and the second channel of the memory array based at least in part on identifying that the pattern generator is operating in the single pattern mode, and Determining whether the memory array includes the one or more errors based at least in part on transmitting the second set of data to the first channel and the second channel.
16. 16. The method as recited in claim 9, further comprising: The circuit is coupled with the memory array using a test collar, wherein identifying whether the pattern generator is operating in the single pattern mode or the multi-pattern mode is based at least in part on coupling the circuit with the memory array.
17. 17. The method as recited in claim 9, further comprising: The memory array is repaired based at least in part on determining that the memory array includes the one or more errors.
18. 18. A non-transitory computer-readable medium storing code comprising instructions that, when executed by a processor of an electronic device, cause the electronic device to: identifying whether a pattern generator of a circuit coupled to the memory array operates in a single pattern mode or a multiple pattern mode; Dividing a data set for testing a memory array into a first portion and a second portion based at least in part on identifying that the pattern generator is operating in the multi-pattern mode; Transmitting the first portion of the data set to a first channel of the memory array and the second portion of the data set to a second channel of the memory array in parallel based at least in part on dividing the data set, and Determining whether the memory array includes one or more errors based at least in part on transmitting the first portion of the data set to the first channel and transmitting the second portion of the data set to the second channel.
19. 19. The non-transitory computer-readable medium of claim 18, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: Identifying an indicator associated with the dataset, wherein identifying whether the pattern generator operates in the single pattern mode or the multi-pattern mode is based at least in part on identifying the indicator.

Description

Pattern generation for multi-channel memory arrays Cross reference This patent application claims priority from U.S. patent application Ser. No. 17/029,718 entitled "Pattern Generation for Multi-channel memory array (PATTERN GENERATION FOR MULTI-CHANNEL MEMORY ARRAY)" filed on even date 9 and 23 in 2020, which is assigned to the present assignee and is expressly incorporated herein by reference in its entirety. Technical Field The technical field relates to pattern generation for multi-channel memory arrays. Background Memory devices are widely used to store information in a variety of electronic devices such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming memory cells within a memory device to various states. For example, a binary memory cell may be programmed to one of two supported states, often indicated by a logic 1 or a logic 0. In some examples, a single memory cell may support more than two states, any of which may be stored. To access the stored information, the component may read or sense at least one stored state in the memory device. To store information, the component may write or program a state in the memory device. There are various types of memory devices and memory cells including magnetic hard disks, random Access Memories (RAMs), read Only Memories (ROMs), dynamic RAMs (DRAMs), synchronous Dynamic RAMs (SDRAM), ferroelectric RAMs (ferams), magnetic RAMs (MRAM), resistive RAMs (RRAM), flash memories, phase Change Memories (PCM), self-selected memories, chalcogenide memory technologies, and the like. The memory cells may be volatile or nonvolatile. Nonvolatile memory such as FeRAM can maintain its stored logic state for a long period of time even in the absence of an external power source. Volatile memory devices, such as DRAMs, may lose their stored state when disconnected from an external power source. Disclosure of Invention An apparatus is described. An apparatus may include a memory array including a first set of memory cells and a second set of memory cells coupled with a first channel and a second set of memory cells coupled with a second channel, a circuit coupled with the memory array and including a pattern generator configured to selectively output a single pattern when operating in a single pattern mode or a plurality of patterns when operating in a multi-pattern mode, and an output response analyzer configured to determine whether the memory array includes one or more errors based at least in part on the patterns output by the pattern generator. A method is described. The method may include identifying whether a pattern generator of a circuit coupled to the memory array is operating in a single pattern mode or a multi-pattern mode, dividing a data set for testing the memory array into a first portion and a second portion based at least in part on identifying that the pattern generator is operating in the multi-pattern mode, transmitting the first portion of the data set to a first channel of the memory array and the second portion of the data set to a second channel of the memory array based at least in part on dividing the data set, and determining whether the memory array includes one or more errors based at least in part on transmitting the first portion to the first channel and the second portion to the second channel. A non-transitory computer-readable medium storing code comprising instructions is described. The instructions, when executed by a processor of the electronic device, may cause the electronic device to identify whether a pattern generator of a circuit coupled with the memory array is operating in a single pattern mode or a multiple pattern mode, divide a data set for testing the memory array into a first portion and a second portion based at least in part on identifying that the pattern generator is operating in the multiple pattern mode, transmit the first portion of the data set to a first channel of the memory array and the second portion of the data set to a second channel of the memory array based at least in part on dividing the data set, and determine whether the memory array includes one or more errors based at least in part on transmitting the first portion to the first channel and the second portion to the second channel. Drawings Fig. 1 illustrates an example of a system supporting pattern generation for a multi-channel memory array in accordance with examples disclosed herein. Fig. 2 illustrates an example of a memory die supporting pattern generation of a multi-channel memory array according to examples disclosed herein. Fig. 3 illustrates an example of a system supporting pattern generation for a multi-channel memory array according to examples disclosed herein. Fig. 4 illustrates an example of circuitry supporting pattern generation for a multi-channel memory array according to examples disclosed herein. Fig. 5 illustrates an example of circuitry supporting pattern gene