CN-114267287-B - Gate driving circuit and display device including the same

Abstract

A gate driving circuit and a display device including the same are provided. The gate driving circuit includes a plurality of cell stages connected to each other, wherein each of the plurality of cell stages includes a first transistor having a lower gate electrode, an upper gate electrode disposed on the lower gate electrode, an active layer disposed between the lower gate electrode and the upper gate electrode, a first electrode contacting a first portion of the active layer, and a second electrode contacting a second portion of the active layer, a first capacitor defined by a first region where the lower gate electrode overlaps the upper gate electrode, and a second capacitor defined by a second region where the upper gate electrode overlaps the first electrode, wherein the upper gate electrode and the lower gate electrode are electrically coupled to each other in the first region where the upper gate electrode overlaps the lower gate electrode to form the first capacitor.

Inventors

• LUO JUNHONG
• Jin jiangnan
• LIN SHENGXUN
• LI YUGEN
• CAO GUISHI

Assignees

• 三星显示有限公司
• 三星显示有限公司

Dates

Publication Date

20260421

Application Date

20210917

Priority Date

20200925

Claims (10)

1. 1. A gate driving circuit for a display device, the gate driving circuit comprising: a plurality of unit stages connected to each other, Wherein each of the plurality of cell stages includes: A first transistor having a lower gate electrode, an upper gate electrode disposed on the lower gate electrode, an active layer disposed between the lower gate electrode and the upper gate electrode, a first electrode contacting a first portion of the active layer, and a second electrode contacting a second portion of the active layer; a first capacitor defined by a first region where the lower gate electrode overlaps the upper gate electrode, and A second capacitor defined by a second region where the upper gate electrode overlaps the first electrode, Wherein the upper gate electrode and the lower gate electrode are electrically coupled to each other in the first region where the upper gate electrode and the lower gate electrode overlap to form the first capacitor, Wherein the first transistor further comprises: A lower gate insulating layer disposed between the lower gate electrode and the active layer; A first insulating layer disposed between the lower gate insulating layer and the upper gate electrode and covering the active layer, the first insulating layer having a first opening and a second opening extending from a top surface of the first insulating layer to a bottom surface of the first insulating layer, wherein the first insulating layer covers the entire top surface of the active layer except for positions where the first opening and the second opening of the first insulating layer are disposed, and An upper gate insulating layer disposed on the first insulating layer and covering the upper gate electrode.
2. 2. The gate drive circuit of claim 1, wherein the first transistor is an NMOS transistor.
3. 3. The gate driving circuit of claim 2, wherein when the voltage at the upper gate electrode is a gate high voltage and the voltage at the second electrode is changed from a gate low voltage to the gate high voltage, The second capacitor bootstraps the voltage at the upper gate electrode and the voltage at the first electrode.
4. 4. The gate driving circuit according to claim 1, wherein the lower gate electrode and the upper gate electrode completely overlap each other in a plan view.
5. 5. The gate drive circuit of claim 1, wherein the active layer includes an opening overlapping the upper gate electrode, the opening extending from a top surface of the active layer to a bottom surface of the active layer.
6. 6. A display device, comprising: a substrate having a display region and a non-display region; a plurality of pixels in the display area, and A gate driving circuit in the non-display region, Wherein the gate driving circuit includes a plurality of unit stages connected to each other, Wherein each of the plurality of cell stages includes: A first transistor including a lower gate electrode, an upper gate electrode disposed on the lower gate electrode, an active layer disposed between the lower gate electrode and the upper gate electrode, a first electrode contacting a first portion of the active layer, and a second electrode contacting a second portion of the active layer; a first capacitor defined by a first region where the lower gate electrode overlaps the upper gate electrode, and A second capacitor defined by a second region where the upper gate electrode overlaps the first electrode, Wherein the upper gate electrode and the lower gate electrode are electrically coupled to each other in the first region where the upper gate electrode and the lower gate electrode overlap to form the first capacitor, Wherein the active layer includes an opening overlapping the upper gate electrode, the opening extending from a top surface of the active layer to a bottom surface of the active layer.
7. 7. The display device according to claim 6, wherein the first transistor is an NMOS transistor.
8. 8. The display device of claim 7, wherein when the voltage at the upper gate electrode is a gate high voltage and the voltage at the second electrode is changed from a gate low voltage to the gate high voltage, The second capacitor bootstraps the voltage at the upper gate electrode and the voltage at the first electrode.
9. 9. The display device according to claim 6, wherein the lower gate electrode and the upper gate electrode completely overlap each other in a plan view.
10. 10. The display device according to claim 6, wherein the first transistor further comprises: A lower gate insulating layer disposed between the lower gate electrode and the active layer; A first insulating layer disposed between the lower gate insulating layer and the upper gate electrode and covering the active layer, the first insulating layer having a first opening and a second opening extending from a top surface of the first insulating layer to a bottom surface of the first insulating layer, wherein the first insulating layer covers the entire top surface of the active layer except for positions where the first opening and the second opening of the first insulating layer are disposed, and An upper gate insulating layer disposed on the first insulating layer and covering the upper gate electrode.

Description

Gate driving circuit and display device including the same Technical Field Embodiments described herein relate to a gate driving circuit, and more particularly, to a display device including a gate driving circuit. Background The display device includes a display area and a non-display area. A plurality of pixels, a plurality of gate lines, and a plurality of data lines may be formed in the display region. A gate driving circuit may be formed in the non-display region. The gate driving circuit may transmit gate signals to the plurality of gate lines. The plurality of pixels may emit light by receiving the data voltage under the control of the gate signal. In order to reduce the area of the gate driving circuit and increase the area of the display region, a double gate transistor may be used in the gate driving circuit. When a double gate transistor is used, a contact for electrically connecting the upper gate electrode and the lower gate electrode may be required. The above information disclosed in this background section is only for the understanding of the background of the inventive concept and, therefore, it may contain information that does not form the prior art. Disclosure of Invention The applicant has appreciated that when a double gate transistor is used, the area of the gate driving circuit may be increased due to the contact portion. When a double gate transistor is used in a gate driving circuit of a display device, there is a need to reduce the area of the gate driving circuit. A gate driving circuit constructed according to the principles and illustrative implementations of the invention and a display device including the gate driving circuit can reduce the area of the gate driving circuit and thus increase the display area available for displaying an image. For example, the gate driving circuit may use a double gate transistor that does not require a contact portion for connecting the upper gate electrode to the lower gate electrode. Accordingly, the gate driving circuit may have a smaller size as compared to the conventional gate driving circuit and display device, and the display device having the gate driving circuit may have a smaller non-display area. The gate driving circuit for a display device according to an embodiment may include a plurality of cell stages subordinate to each other, wherein each of the plurality of cell stages includes a first transistor including a lower gate electrode, an upper gate electrode disposed on the lower gate electrode, an active layer disposed between the lower gate electrode and the upper gate electrode, a first electrode contacting a first portion of the active layer, and a second electrode contacting a second portion of the active layer, the first capacitor being defined by a first region where the lower gate electrode overlaps the upper gate electrode, and the second capacitor being defined by a second region where the upper gate electrode overlaps the first electrode, wherein the upper gate electrode and the lower gate electrode are electrically coupled to each other in the first region where the upper gate electrode overlaps the lower gate electrode to form the first capacitor. The first transistor may be an NMOS transistor (simply referred to as NMOS, and PMOS is similar thereto). When the voltage at the upper gate electrode is a gate high voltage and the voltage at the second electrode is changed from a gate low voltage to a gate high voltage, the second capacitor may bootstrap the voltage at the upper gate electrode and the voltage at the first electrode. The first transistor may be a PMOS transistor. When the voltage at the upper gate electrode is a gate low voltage and the voltage at the second electrode is changed from a gate high voltage to a gate low voltage, the second capacitor may bootstrap the voltage at the upper gate electrode and the voltage at the first electrode. The lower gate electrode and the upper gate electrode may completely overlap each other in a plan view. The active layer may include an opening overlapping the upper gate electrode. The first transistor may include a lower gate insulating layer disposed between the lower gate electrode and the active layer, a first insulating layer disposed between the lower gate insulating layer and the upper gate electrode and covering the active layer, and an upper gate insulating layer disposed on the first insulating layer and covering the upper gate electrode. Each of the plurality of cell stages may include a second transistor operable in response to a previous output signal from a previous cell stage, a third transistor discharging the second capacitor in response to a next output signal from a next cell stage, and a fourth transistor discharging the output signal in response to the next output signal. The plurality of cell stages may be connected to each other such that an output of a corresponding one of the plurality of cell stages is connected to an input of another one of th