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CN-114267725-B - Semiconductor device with a semiconductor device having a plurality of semiconductor chips

CN114267725BCN 114267725 BCN114267725 BCN 114267725BCN-114267725-B

Abstract

The invention relates to a semiconductor device, which aims to ensure an operation area in an RC-IGBT and reduce recovery loss. The occupancy ratio of the n + -type source layer (13) in the unit area of the boundary region (50) is smaller than the occupancy ratio of the n + -type source layer (13) in the unit area of the IGBT region (10) when viewed in plan view of the RC-IGBT (100, 101), and the occupancy ratio of the p + -type contact layer (14) in the unit area of the boundary region (50) is smaller than the occupancy ratio of the p + -type contact layer (14) in the unit area of the IGBT region (20).

Inventors

  • SONEDA SHINYA
  • 11
  • Xiangyu Otsuka

Assignees

  • 三菱电机株式会社

Dates

Publication Date
20260505
Application Date
20210922
Priority Date
20201001

Claims (11)

  1. 1. A semiconductor device having a semiconductor substrate including a drift layer of a1 st conductivity type, the semiconductor device being arranged such that an IGBT region and a diode region sandwich a boundary region therebetween in a plan view, The semiconductor substrate has a 1 st main surface and a2 nd main surface opposite to the 1 st main surface, The IGBT region and the boundary region have: A base layer of a2 nd conductivity type formed on the 1 st main surface side of the drift layer; a1 st conductive source layer formed on the 1 st main surface side of the base layer; A1 st contact layer of the 2 nd conductivity type formed adjacent to the source layer on the 1 st main surface side of the base layer, the 2 nd conductivity type impurity concentration being higher than that of the base layer, and A collector layer of the 2 nd conductivity type formed on the 2 nd main surface side of the drift layer, The diode region has: an anode layer of the 2 nd conductivity type formed on the 1 st main surface side of the drift layer, and A cathode layer of the 1 st conductivity type formed on the 2 nd main surface side of the drift layer, The source layer in the unit area of the boundary region has a smaller occupancy ratio than the source layer in the unit area of the IGBT region in a plan view, the 1 st contact layer in the unit area of the boundary region has a smaller occupancy ratio than the 1 st contact layer in the unit area of the IGBT region, In the boundary region, the base layer is not formed in at least a part of a region of the 1 st main surface where the source layer or the 1 st contact layer is not formed.
  2. 2. The semiconductor device according to claim 1, wherein, The diode region has a 2 nd contact layer of a 2 nd conductivity type on the 1 st main surface side of the anode layer, the 2 nd contact layer of the 2 nd conductivity type having a higher impurity concentration of the 2 nd conductivity type than the anode layer, The occupation ratio of the 1 st contact layer in the unit area of the boundary region is smaller than the occupation ratio of the 2 nd contact layer in the unit area of the diode region in a plan view.
  3. 3. The semiconductor device according to claim 1, wherein, The IGBT region, the diode region, and the boundary region further have: An interlayer insulating film formed on the 1 st main surface of the semiconductor substrate and having a contact hole exposing the 1 st main surface, and An emitter electrode formed on the 1 st main surface of the semiconductor substrate with the interlayer insulating film interposed therebetween, In the boundary region, the base layer is exposed in a region of the 1 st main surface where the source layer or the 1 st contact layer is not formed, and the exposed base layer is in electrical contact with the emitter electrode via the contact hole.
  4. 4. The semiconductor device according to claim 2, wherein, The IGBT region, the diode region, and the boundary region further have: An interlayer insulating film formed on the 1 st main surface of the semiconductor substrate and having a contact hole exposing the 1 st main surface, and An emitter electrode formed on the 1 st main surface of the semiconductor substrate with the interlayer insulating film interposed therebetween, In the boundary region, the base layer is exposed in a region of the 1 st main surface where the source layer or the 1 st contact layer is not formed, and the exposed base layer is in electrical contact with the emitter electrode via the contact hole.
  5. 5. The semiconductor device according to any one of claims 1 to 4, wherein, The occupation ratio of the source layer per unit area of the boundary region becomes gradually smaller from the IGBT region side toward the diode region side in a plan view.
  6. 6. The semiconductor device according to claim 1, wherein, The anode layer has a2 nd conductivity type impurity concentration lower than a2 nd conductivity type impurity concentration of the base layer.
  7. 7. The semiconductor device according to claim 6, wherein, In the boundary region, the anode layer is formed in a region where the base layer is not formed, of the region where the source layer or the 1 st contact layer is not formed of the 1 st main surface.
  8. 8. The semiconductor device according to claim 2, wherein, The IGBT region and the boundary region have a plurality of trench gates extending from the 1 st main surface through the base layer to the drift layer, extending in the 1 st direction, being arranged in the 2 nd direction orthogonal to the 1 st direction, The diode region has a plurality of 1 st dummy trench gates, and the 1 st dummy trench gates extend in the 1 st direction and are aligned in the 2 nd direction from the 1 st main surface, extend through the anode layer, and reach the drift layer.
  9. 9. The semiconductor device according to claim 8, wherein, The boundary region is distinguished as: an IGBT operation region in which the source layer is arranged to perform IGBT operation, and An IGBT non-operation region in which the source layer is not arranged, and in which IGBT operation is not performed, The IGBT non-operation region further includes a2 nd dummy trench gate formed in at least a part of the 1 st main surface where the base layer is not formed, reaching the drift layer from the 1 st main surface, The 2 nd dummy trench gate is in contact with at least a part of the 1 st dummy trench gate of the diode region and the plurality of trench gates arranged in the IGBT non-operation region.
  10. 10. The semiconductor device according to claim 8 or 9, wherein, The 2 nd contact layer of the diode region is disposed so as to avoid the diode region on a line along the 2 nd direction from a region of the boundary region where the source layer is disposed.
  11. 11. The semiconductor device according to any one of claims 1 to 4, wherein, The width of the boundary region is greater than the thickness of the semiconductor substrate.

Description

Semiconductor device with a semiconductor device having a plurality of semiconductor chips Technical Field The present invention relates to a reverse-conducting semiconductor device (RC-IGBT) provided with a flywheel diode and an insulated gate bipolar transistor (IGBT: insulated Gate Bipolar Transistor) at the same time. Background The RC-IGBT has a problem in that holes are injected from the IGBT region to the diode region due to high hole injection efficiency of the IGBT cell, whereby recovery loss is large. To solve this problem, conventionally, a boundary region is provided between an IGBT region and a diode region, and the boundary region has a structure in which a collector layer is arranged immediately below a diode cell (for example, patent document 1). Patent document 1 Japanese patent application laid-open No. 2018-073911 However, the boundary region does not operate as an IGBT or a diode, and therefore becomes an ineffective region that does not actively participate in the energization operation. Therefore, in a limited element region, a boundary region cannot be sufficiently secured in order to secure an effective operation region required for securing sufficient power-on capability, and there is a problem that recovery loss cannot be reduced. Disclosure of Invention The present invention has been made to solve the above-described problems, and an object of the present invention is to ensure an operation region in an RC-IGBT and reduce recovery loss. A semiconductor device of the present invention includes a semiconductor substrate including a drift layer of a 1 st conductivity type, the semiconductor substrate including a 1 st main surface and a2 nd main surface opposite to the 1 st main surface, the semiconductor substrate including a boundary region interposed therebetween in a plan view, the IGBT region and the boundary region including a2 nd conductivity type base layer formed on the 1 st main surface side of the drift layer, a 1 st conductivity type source layer formed on the 1 st main surface side of the base layer, a2 nd conductivity type 1 contact layer formed adjacent to the source layer on the 1 st main surface side of the base layer, the 2 nd conductivity type impurity concentration being higher than the base layer, and a2 nd conductivity type collector layer formed on the 2 nd main surface side of the drift layer, the diode region including a2 nd conductivity type anode layer formed on the 1 st main surface side of the drift layer, and a 1 st conductivity type source layer formed on the 1 st main surface side of the drift layer, the ratio occupied by the 1 st conductivity type source layer being smaller than the area occupied by the 1 st conductivity type source layer in the boundary region in the unit area of the area ratio 1 st area of the IGBT layer. ADVANTAGEOUS EFFECTS OF INVENTION According to the semiconductor device of the present invention, since the occupancy ratio of the 1 st contact layer in the unit area of the boundary region is smaller than the occupancy ratio of the 1 st contact layer in the unit area of the IGBT region, the operation region of the IGBT can be ensured, and the recovery loss can be reduced. Drawings Fig. 1 is a top view of a stripe-type RC-IGBT. Fig. 2 is a top view of an island-type RC-IGBT. Fig. 3 is a top view of the IGBT region. Fig. 4 is a cross-sectional view of the IGBT area at line A-A' of fig. 3. Fig. 5 is a cross-sectional view of the IGBT region at line B-B' of fig. 3. Fig. 6 is a top view of a diode region. Fig. 7 is a cross-sectional view of the diode region at line C-C' of fig. 6. Fig. 8 is a cross-sectional view of the diode region at line D-D' of fig. 6. Fig. 9 is a plan view of an IGBT region, a boundary region, and a diode region in the RC-IGBT of embodiment 1. Fig. 10 is a cross-sectional view of the IGBT region at the O-O' line of fig. 9. Fig. 11 is a cross-sectional view of the boundary region of embodiment 1 at the line P-P' of fig. 9. Fig. 12 is a cross-sectional view of the diode region at line Q-Q' of fig. 9. Fig. 13 is a cross-sectional view of the IGBT region, the boundary region, and the diode region at line G-G' of fig. 9. Fig. 14 is a cross-sectional view of the IGBT region and the terminal region at line E-E' of fig. 1 or 2. Fig. 15 is a cross-sectional view of the diode region and the end region at line F-F' of fig. 1 or 2. Fig. 16 is a plan view of an IGBT region, a boundary region, and a diode region in the RC-IGBT of embodiment 2. Fig. 17 is a plan view of an IGBT region, a boundary region, and a diode region in the RC-IGBT of embodiment 3. Fig. 18 is a cross-sectional view of the boundary region of embodiment 3 at line P-P' of fig. 17. Fig. 19 is a plan view of an IGBT region, a boundary region, and a diode region in the RC-IGBT of embodiment 4. Fig. 20 is a cross-sectional view of the boundary region of embodiment 4 at line P-P' of fig. 19. Fig. 21 is a plan view of an IGBT region, a boundary region, and a diode r