CN-114283866-B - TLC NAND flash memory decoding method, device, system and medium

CN114283866BCN 114283866 BCN114283866 BCN 114283866BCN-114283866-B

Abstract

The application provides a TLC NAND flash memory decoding method, a device, a system and a medium, wherein the method comprises the following steps: and performing multiple times of reading operation on the first logical page of the TLC NAND flash memory by adopting the reading voltage to obtain multiple times of reading results, performing the same or the same reading results to obtain initial decoding results, obtaining initial LLR values respectively corresponding to each distribution state of the first logical page of the TLC NAND flash memory according to the initial decoding results, correcting the initial LLR values according to the multiple times of reading results to obtain corrected LLR values, and decoding the TLC NAND flash memory according to the corrected LLR values. The LLR value is corrected by utilizing the data of the logical page in the same physical page, and the LLR value is not corrected by utilizing the data of other logical pages, so that the TLC NAND flash memory is correctly decoded, the realization is simple, and the efficiency and the user experience are improved.

Inventors

WANG KEN
YU XIAOLEI
LI QIANHUI
YANG LIU
HE JING
WANG XIANLIANG
ZHANG BO
HUO ZONGLIANG
YE TIANCHUN

Assignees

中国科学院微电子研究所

Dates

Publication Date: 20260505
Application Date: 20211223

Claims (6)

1. A TLC NAND flash decoding method, comprising: Performing multiple reading operations on a first logical page of the TLC NAND flash memory by using a reading voltage to obtain multiple reading results, wherein one physical page in the TLC NAND flash memory comprises a lower page, a middle page and an upper page, the TLC NAND flash memory comprises E, P-P7 eight distributed states, and when the first logical page is the lower page, the multiple reading operations on the first logical page of the TLC NAND flash memory by using the reading voltage are performed to obtain multiple reading results, and the multiple reading results comprise performing the reading operations by using a first reading voltage between the E state and the P1 state to obtain a first reading result, and performing the reading operations by using a fifth reading voltage between the P4 state and the P5 state to obtain a fifth reading result; Carrying out the same or obtaining an initial decoding result among the reading results; obtaining initial LLR values corresponding to each distribution state of the first logical page of the TLC NAND according to the initial decoding result; Correcting the initial LLR value according to the multiple reading results to obtain a corrected LLR value, wherein the correcting of the initial LLR value according to the multiple reading results comprises the steps of obtaining position information of each distribution state corresponding to the multiple reading results; And decoding the TLC NAND flash memory according to the corrected LLR value.
2. The method of claim 1, wherein the correcting the initial LLR value based on the multiple read results to obtain a corrected LLR value, and wherein the performing multiple read operations on the second logical page of the TLC NAND flash memory using the read voltage to obtain multiple read results are performed in parallel.
3. A TLC NAND flash decoding device, comprising: The device comprises a first logical page reading unit, a fifth reading unit and a first logical page reading unit, wherein the first logical page reading unit is used for carrying out multiple times of reading operation on a first logical page of a TLC NAND flash memory by using a reading voltage to obtain multiple times of reading results, one physical page in the TLC NAND flash memory comprises a lower page, a middle page and an upper page, the TLC NAND flash memory comprises E, P-P7 eight distributed states, when the first logical page is the lower page, the first logical page reading unit comprises a first reading unit used for carrying out the reading operation by using the first reading voltage between the E state and the P1 state to obtain the first reading result, and the fifth reading unit is used for carrying out the reading operation by using the fifth reading voltage between the P4 state and the P5 state to obtain the fifth reading result; an exclusive nor unit for exclusive nor the read results to obtain an initial decoding result; an initial LLR value obtaining unit, configured to obtain initial LLR values corresponding to each distribution state of the first logical page of the TLC NAND according to the initial decoding result; The correction LLR value acquisition unit comprises a position information acquisition unit, a correction LLR value acquisition subunit and a correction unit, wherein the position information acquisition unit is used for acquiring position information of each distribution state corresponding to the multiple reading results; and the decoding unit is used for decoding the TLC NAND flash memory according to the corrected LLR value.
4. A device according to claim 3, characterized in that the device further comprises: The second logic page reading unit is used for performing multiple reading operations on the second logic page of the TLC NAND flash memory by adopting the reading voltage to obtain multiple reading results; and the parallel operation unit is used for enabling the corrected LLR value acquisition unit and the second logic page reading unit to operate in parallel.
5. A TLC NAND flash decoding system, comprising: A memory for storing a computer program; a processor for implementing the steps of the TLC NAND flash decoding method as claimed in any one of claims 1-2 when executing said computer program.
6. A computer readable storage medium, characterized in that it has stored thereon a computer program which, when processed and executed, implements the steps of the TLC NAND flash decoding method according to any of claims 1-2.

Description

TLC NAND flash memory decoding method, device, system and medium Technical Field The application relates to the technical field of semiconductors, in particular to a TLC NAND flash memory decoding method and device. Background The characteristics of the semiconductor memory device may be volatile or nonvolatile, and although the volatile semiconductor memory device may perform a read operation and a write operation at high speed, contents stored in the volatile semiconductor memory device may be lost in a power-off state. In contrast, a nonvolatile semiconductor memory device is characterized in that stored contents are retained regardless of whether power is applied or not. Flash memory devices (Flash memory) are examples of typical nonvolatile semiconductor memory devices, which can be widely used as data storage media. The nonvolatile memory includes a plurality of memory cells arranged in an array for storing data. The memory unit is divided into a plurality of blocks (blocks), each block is divided into a plurality of pages (pages), and operations such as reading, writing, verifying, clearing and the like of the nonvolatile memory can be performed by taking the pages as units. When the nonvolatile memory stores information, it is necessary to encode data, write the encoded data into memory cells in the memory array, and perform a decoding operation when reading the encoded data. In NAND FLASH memory devices, NLC NAND FLASH such as SLC (Single-layer cell) and MLC (double-layer cell) and TLC (triple-layer cell, trinary-LEVEL CELL) are mainly classified, and different numbers of electrons can be injected into the floating gate or charge trapping layer of the NAND FLASH memory device to obtain different threshold voltages, so as to represent different logic states, and when reading data, for example, double-layer cell (Multi-LEVEL CELL, MLC) NAND FLASH, four logic states are distinguished by applying 3 different read voltages to the gate. With the advent of multi-layer cells NAND FLASH such as TLC, the distribution states are further compressed, TLC has 2 3 =8 distribution states along the threshold voltage distribution, and the distribution states overlap each other, so that the problem of error code in reading data is more and more serious, so that each large manufacturer is researching various auxiliary decoding operations to enhance decoding performance, where the LLR (log likelihood ratio ) correction technique is a method that can greatly enhance decoding capability with the advent of NLC NAND FLASH, and conventional LLR correction technique generally corrects LLR values by data information of other logical pages in the same physical page, which requires that the reading operation must be continuous and the data of other logical pages in the same physical page be kept as correct as possible, which is difficult to implement, has low efficiency, and causes poor user experience. Disclosure of Invention Accordingly, the present application is directed to a TLC NAND flash decoding method, apparatus, system and medium, which can simply and quickly correct LLR values, and improve the user experience while implementing correct decoding of TLC NAND flash. In order to achieve the above purpose, the application has the following technical scheme: in a first aspect, an embodiment of the present application provides a TLC NAND flash decoding method, including: performing multiple reading operations on a first logical page of the TLC NAND flash memory by adopting a reading voltage to obtain multiple reading results; Carrying out the same or obtaining an initial decoding result among the reading results; obtaining initial LLR values corresponding to each distribution state of the first logical page of the TLC NAND according to the initial decoding result; correcting the initial LLR value according to the multiple reading results to obtain a corrected LLR value; And decoding the TLC NAND flash memory according to the corrected LLR value. In one possible implementation, the correcting the initial LLR value according to the multiple reading results to obtain a corrected LLR value includes: acquiring position information of each distribution state corresponding to the multiple reading results; and correcting the first LLR value according to the position information to obtain a corrected LLR value. In one possible implementation, one physical page in the TLC NAND flash memory comprises a lower page, a middle page and an upper page, wherein the TLC NAND flash memory comprises E, P-P7 eight distribution states; And performing multiple reading operations on the first logical page of the TLC NAND flash memory by adopting the reading voltage to obtain multiple reading results when the first logical page is the lower page, wherein the method comprises the following steps of: And performing a read operation by using a first read voltage between the E state and the P1 state to obtain a first read result, and performing a read o