CN-114301454-B - Fractional divider, numerically controlled oscillator and phase-locked loop circuit

Abstract

A fractional frequency divider, a digitally controlled oscillator, a phase locked loop circuit are provided. The fractional divider includes a multi-modulus divider for generating a first divided clock based on an input clock and a division coefficient sequence, a first flip-flop for generating a second divided clock based on the first divided clock, a second flip-flop for generating a third divided clock based on the first divided clock, a first multiplexer for selecting one of the first divided clock and the second divided clock as a first output divided clock, and a second multiplexer for selecting one of the second divided clock and the third divided clock as a second output divided clock.

Inventors

• NIU YAOQI
• SONG HONGDONG

Assignees

• 思瑞浦微电子科技(上海)有限责任公司

Dates

Publication Date

20260508

Application Date

20211230

Claims (9)

1. 1. A fractional divider comprising: a multi-modulus divider for generating a first divided clock based on an input clock and a division coefficient sequence; a first flip-flop for generating a second divided clock based on the first divided clock; a second flip-flop for generating a third divided clock based on the first divided clock; a first multiplexer for selecting one of the first divided clock and the second divided clock as a first output divided clock, and And a second multiplexer for selecting one of the second divided clock and the third divided clock as a second output divided clock, wherein the first multiplexer and the second multiplexer are for performing clock selection based on the same clock selection signal.
2. 2. The fractional divider of claim 1, wherein the first flip-flop is to receive an inverse of the input clock as a clock control signal and the second flip-flop is to receive the input clock as a clock control signal.
3. 3. A digitally controlled oscillator, comprising: A fractional divider, the fractional divider comprising: a multi-modulus divider for generating a first divided clock based on an input clock and a division coefficient sequence; a first flip-flop for generating a second divided clock based on the first divided clock; a second flip-flop for generating a third divided clock based on the first divided clock; a first multiplexer for selecting one of the first divided clock and the second divided clock as a first output divided clock, and A second multiplexer for selecting one of the second divided clock and the third divided clock as a second output divided clock, wherein the first multiplexer and the second multiplexer are for performing clock selection based on the same clock selection signal; A digital time converter for generating an output clock based on the first output divided clock and the second output divided clock, and for performing phase error correction on the output clock according to a phase error signal; a modulator for generating the frequency division coefficient sequence and the frequency error signal, and And the accumulator is used for accumulating the frequency error signals to obtain the phase error signals.
4. 4. A digitally controlled oscillator as claimed in claim 3 wherein the modulator is further for generating the clock select signal.
5. 5. A digitally controlled oscillator according to claim 3, wherein the digital time converter is a phase interpolator based digital time converter.
6. 6. The digitally controlled oscillator of any one of claims 3 to 5, wherein the first flip-flop is to receive an inverted signal of the input clock as a clock control signal, and wherein the second flip-flop is to receive the input clock as a clock control signal.
7. 7. The digitally controlled oscillator of any one of claims 3 to 5, wherein the output clock has a period resolution of 0.5 times the input clock.
8. 8. A phase locked loop circuit comprising: A phase comparator for outputting an error signal based on a reference clock and a feedback clock, the error signal indicative of a phase difference between the reference clock and the feedback clock; A loop filter for loop filtering the error signal; a voltage controlled oscillator for generating a voltage controlled oscillation signal based on the error signal after loop filtering, and The digitally controlled oscillator according to any one of claims 4 to 7, for receiving the voltage controlled oscillation signal as the input clock and for generating the output clock as the feedback clock.
9. 9. The phase-locked loop circuit of claim 8, wherein the phase comparator is further configured to output a late signal based on the reference clock and the feedback clock, the late signal indicating a temporal order of the reference clock and the feedback clock relative to each other, wherein the modulator is further configured to generate a clock selection signal, and wherein the phase-locked loop circuit further comprises: a first error estimation circuit for determining a clock phase error from the late signal and the clock select signal; a first multiplier for multiplying the clock phase error with the clock select signal to obtain a clock error signal; a second error estimation circuit for determining a gain error from the late signal and the phase error signal; a first adder for adding the clock error signal and the phase error signal to obtain an added error signal, and A second multiplier for multiplying the gain error with the added error signal for output to the digital-to-time converter for full-amplitude error correction by the digital-to-time converter.

Description

Fractional divider, numerically controlled oscillator and phase-locked loop circuit Technical Field The present disclosure relates to the field of circuit technology, and in particular, to a fractional frequency divider, a digitally controlled oscillator, and a phase locked loop circuit. Background In modern electronic system designs, divider circuits are a very important circuit block. The divider circuit may divide the higher frequency signal to obtain the desired low frequency signal and may be divided into an integer divider or a fractional divider depending on the division factor. The frequency divider circuit has wide application, for example, can be applied to a digital controlled oscillator circuit, a phase locked loop circuit and the like. Disclosure of Invention According to an aspect of the present disclosure, there is provided a fractional divider including a multi-modulus divider for generating a first divided clock based on an input clock and a series of division coefficients, a first flip-flop for generating a second divided clock based on the first divided clock, a second flip-flop for generating a third divided clock based on the first divided clock, a first multiplexer for selecting one of the first divided clock and the second divided clock as a first output divided clock, and a second multiplexer for selecting one of the second divided clock and the third divided clock as a second output divided clock. According to another aspect of the present disclosure, there is provided a numerically controlled oscillator including a fractional divider including a multi-modulus divider for generating a first divided clock based on an input clock and a sequence of frequency dividing coefficients, a first flip-flop for generating a second divided clock based on the first divided clock, a second flip-flop for generating a third divided clock based on the first divided clock, a first multiplexer for selecting one of the first divided clock and the second divided clock as a first output divided clock, and a second multiplexer for selecting one of the second divided clock and the third divided clock as a second output divided clock, a digital-to-time converter for generating an output clock based on the first output clock and the second output divided clock and for phase error signal, a first multiplexer for selecting one of the first divided clock and the second divided clock as a first output divided clock, and for phase error signal modulating the output clock, a frequency multiplexer for generating the frequency dividing coefficients and a frequency error signal, and an accumulator for the error signal. According to yet another aspect of the present disclosure, there is provided a phase locked loop circuit including a phase comparator for outputting an error signal based on a reference clock and a feedback clock, the error signal indicating a phase difference between the reference clock and the feedback clock, a loop filter for loop filtering the error signal, a voltage controlled oscillator for generating a voltage controlled oscillation signal based on the loop filtered error signal, and a digital controlled oscillator according to an embodiment of the present disclosure for receiving the voltage controlled oscillation signal as the input clock and for generating the output clock as the feedback clock. These and other aspects of the disclosure will be apparent from and elucidated with reference to the embodiments described hereinafter. Drawings Further details, features and advantages of the present disclosure are disclosed in the following description of exemplary embodiments, with reference to the following drawings, wherein: fig. 1A shows a schematic circuit diagram of a digitally controlled oscillator in the related art. Fig. 1B to 1D show schematic diagrams of a digital-to-time converter in the related art. Fig. 2A illustrates an example fractional divider according to an embodiment of the present disclosure. Fig. 2B illustrates an example timing diagram of a divided clock in a fractional divider according to an embodiment of the present disclosure. Fig. 3 illustrates an example digitally controlled oscillator according to an embodiment of this disclosure. Fig. 4 illustrates an example phase-locked loop circuit according to an embodiment of this disclosure. Detailed Description It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure. The t