CN-114301465-B - Sigma-Delta analog-to-digital converter

CN114301465BCN 114301465 BCN114301465 BCN 114301465BCN-114301465-B

Abstract

The invention discloses a Sigma-Delta analog-to-digital converter which comprises a loop filter module, a first feedback circuit, a second feedback circuit and a quantizer, wherein the loop filter module comprises summing nodes connected in a cascading mode, the first feedback circuit is connected between the input end of the summing node corresponding to a first-stage integrator and the output end of the quantizer, the first feedback circuit is used for performing first time expansion processing on a quantized output signal output by the quantizer and converting the quantized output signal into a first feedback signal, the second feedback circuit is connected between the summing node corresponding to a last-stage integrator and the output end of the quantizer, the second feedback circuit is used for performing second time expansion processing on the quantized output signal output by the quantizer and converting the quantized output signal into a second feedback signal, and then transmitting the second feedback signal to the summing node corresponding to the last-stage integrator.

Inventors

LIANG JUNHAO
ZHAO WEIBING

Assignees

珠海一微半导体股份有限公司

Dates

Publication Date: 20260505
Application Date: 20211229

Claims (14)

1. A Sigma-Delta analog-to-digital converter, characterized in that the Sigma-Delta analog-to-digital converter comprises a loop filter module, a first feedback circuit and a quantizer; The loop filter module comprises summing nodes and integrators, wherein the integrators exist in the loop filter module in a cascade connection mode, and the input end of each integrator is connected with a corresponding summing node to form a corresponding summing node of the integrator; The first feedback circuit is connected between the input end of the summing node corresponding to the first-stage integrator and the output end of the quantizer, and is used for performing first time extension processing on the quantized output signal output by the quantizer and converting the quantized output signal into a first feedback signal, and then transmitting the first feedback signal to the input end of the summing node corresponding to the first-stage integrator; The Sigma-Delta analog-to-digital converter further comprises a second feedback circuit; The second feedback circuit is connected between the summing node corresponding to the last integrator and the output end of the quantizer, and is used for performing second time extension processing on the quantized output signal output by the quantizer and converting the quantized output signal into a second feedback signal, and transmitting the second feedback signal to the summing node corresponding to the last integrator, wherein the second time extension processing performed by the second feedback circuit is used for compensating the first time extension processing performed by the first feedback circuit.
2. The Sigma-Delta analog-to-digital converter of claim 1, wherein said quantizer, said first feedback circuit and loop filter module are cascaded to form a feedback loop and to form a first loop filter function, wherein said first loop filter function is obtained by changing an original transfer function by said first feedback circuit and is a transfer function belonging to the Sigma-Delta analog-to-digital converter; The quantizer, the second feedback circuit and the loop filter module are cascaded to form a compensation loop and form a second loop filter function, wherein the second loop filter function is used for compensating the first loop filter function so as to adjust the transmission function of the Sigma-Delta analog-to-digital converter to be an original transmission function.
3. The Sigma-Delta analog-to-digital converter of claim 2, wherein said first feedback circuit comprises a first feedback DAC and a first filter; The input end of the first filter is connected with the output end of the quantizer, the input end of the first feedback DAC is connected with the output end of the first filter, the output end of the first feedback DAC is connected with the input end of a summing node corresponding to the first-stage integrator, the first filter is used for carrying out time delay processing with the frequency of the quantized output signal output by the quantizer being a first preset number of taps, wherein the time delay processing with the frequency of the first preset number of taps carried out by the first filter is the first time extension processing, so that the accuracy of the quantized output signal filtered by the first filter is higher than that of the quantized output signal; The first feedback DAC is used for converting the quantized output signal filtered by the first filter into a first feedback signal in real time, and transmitting the first feedback signal to the input end of the summing node corresponding to the first-stage integrator so as to change the original transfer function.
4. A Sigma-Delta analog-to-digital converter according to claim 3, characterized in that the input of the summing node corresponding to each integrator is connected to the output of said first feedback DAC, except for the summing node corresponding to the first integrator.
5. The Sigma-Delta analog-to-digital converter of claim 3, wherein said second feedback circuit comprises a second feedback DAC and a second filter, the number of taps of the second filter being equal to a second preset number of taps; The second filter is used for carrying out time delay processing with the frequency of the quantized output signal output by the quantizer being a second preset tap number, wherein the time delay processing with the frequency of the second filter being the second preset tap number is the second time extension processing so as to compensate the first filter, and the accuracy of the quantized output signal filtered by the second filter is higher than that of the quantized output signal; the second feedback DAC is used for converting the quantized output signal filtered by the second filter into a second feedback signal, and transmitting the second feedback signal to the input end of the summing node corresponding to the last integrator, so that the quantized output signal is expanded into an analog signal with a delay compensation effect, and the transmission function of the Sigma-Delta analog-digital converter is adjusted to be the original transmission function.
6. The Sigma-Delta analog-to-digital converter of claim 5, wherein a first filter coefficient is provided inside said first filter, and wherein said first filter introduces a first filter transfer function in said first feedback circuit, wherein said first filter coefficient is a parameter belonging to said first filter transfer function; The second filter is internally provided with a second filter coefficient, and correspondingly, the second filter introduces a second filter transfer function into the second feedback circuit, wherein the second filter coefficient is a parameter belonging to the second filter transfer function; The first filter coefficient and the second filter coefficient are matched with each other, so that the signal change caused by the first filter transfer function in the Sigma-Delta analog-to-digital converter and the signal caused by the second filter transfer function in the Sigma-Delta analog-to-digital converter are mutually offset, and the delay state of the transfer function of the Sigma-Delta analog-to-digital converter is controlled to be the same as the delay state of the original transfer function.
7. The Sigma-Delta analog-to-digital converter of claim 5, wherein filter coefficients internally set by said first filter and filter coefficients internally set by said second filter are not exactly the same, wherein the number of filter coefficients internally set by said first filter and the number of filter coefficients internally set by said second filter are both equal to a preset number of taps; the implementation structure of the first filter and the implementation structure of the second filter belong to the same preset filter structure.
8. The Sigma-Delta analog-to-digital converter of claim 7, wherein said predetermined filter structure comprises m delay cells, a coefficient matching module, and an accumulator; The m delay units are connected in series and are used for generating m digital input signals representing different delays, wherein m is a positive integer; The coefficient matching module is used for providing a matched filter coefficient for each digital input signal, multiplying each digital input signal by the matched filter coefficient, and outputting a corresponding product; and the accumulator is used for adding each product output by the coefficient matching module to obtain a filtered quantized output signal.
9. The Sigma-Delta analog-to-digital converter of any of claims 1 to 8, wherein said loop filter module comprises an N-stage summing node, an N-stage integrator, and a final operational amplifier; the output end of the final-stage integrator is connected with the input end of the final-stage operational amplifier, the output end of the final-stage operational amplifier is connected with the input end of the quantizer, and the output end of the final-stage operational amplifier is used for outputting a pre-feedback analog signal; Each stage of summing node has a first input, a second input and an output; The first input end of the ith summing node is connected with the output end of the ith-1 level integrator, the first input end of the ith summing node is used for receiving the ith-1 level integral analog signal output by the ith-1 level integrator, the second input end of the ith summing node is connected with the output end of the final operational amplifier, the second input end of the ith summing node is used for receiving the prefeedback analog signal output by the final operational amplifier, the output end of the ith summing node is connected with the input end of the ith level integrator, and the output end of the ith summing node is used for outputting the ith summing analog signal to the input end of the ith level integrator, wherein the ith summing analog signal is the sum of the ith-1 level integral analog signal and the prefeedback analog signal output by the final operational amplifier; The ith integrator is used for integrating the ith summation analog signal and outputting an ith integration analog signal; the i-1-stage integrator is used for integrating the output signal of the i-1-stage summing node to obtain the i-1-stage integrated analog signal; Wherein N is a positive integer, i is an integer greater than 1, and i is an integer less than or equal to N-1.
10. The Sigma-Delta analog-to-digital converter of claim 9, wherein a first input of the first stage summing node is configured to receive an analog input signal, and a second input of the first stage summing node is configured to receive a first feedback signal output by said first feedback circuit; the first-stage summing node is used for summing the analog signal and a first feedback signal provided by the first feedback circuit, and configuring the sum value as the first-stage summed analog signal; The first-stage integrator is used for receiving and integrating the first-stage summation analog signal to obtain a first-stage integration analog signal.
11. The Sigma-Delta analog-to-digital converter of claim 10, wherein a first input of an nth stage summing node is coupled to an output of an nth-1 stage integrator, the first input of the nth stage summing node being configured to receive an nth-1 stage integrated analog signal output by the nth-1 stage integrator; the output end of the nth summing node is used for outputting the nth summing analog signal to the nth integrator.
12. The Sigma-Delta analog-to-digital converter of claim 11, wherein the nth summing node has N-1 preset inputs in addition to the first input and the second input; In the first-stage summing node to the N-1 th-stage summing node, the signal input to the first input end of each stage of summing node is further configured to be input to a corresponding preset input end in the N-th stage of summing node; The N-th summation node is used for summing the N-1-th integration analog signal, the second feedback signal and the signals input by each preset input end, and configuring the summation value as an N-th summation analog signal; And the nth stage integrator is used for receiving and integrating the nth stage summation analog signal to obtain an nth stage integration analog signal.
13. The Sigma-Delta analog-to-digital converter of claim 12, wherein each integrator is a continuous-time structure for integrating the input signal via the continuous-time structure; The circuit comprises a first-stage summing node, a second-stage summing node, a third-stage summing node, a fourth-stage summing node, a fifth-stage summing node, a sixth-stage summing node, a seventh-stage summing node and a fourth-stage summing node, wherein the inside of each first-stage integrator comprises a branch resistor and a preconfigured operational amplifier, and the output end of the branch resistor is connected with the input end of the preconfigured operational amplifier; Wherein the input end of the preconfigured operational amplifier is the input end of the affiliated integrator; The first input end of each stage of summing node is an input end of one branch resistor corresponding to the inside of the stage of integrator, and the second input end of each stage of summing node is an input end of the other branch resistor corresponding to the inside of the stage of integrator; Each preset input end of the final-stage summing node is an input end of a corresponding branch resistor in the final-stage integrator.
14. The Sigma-Delta analog-to-digital converter of claim 12, wherein N is a value of 3; When the quantization bit number of the quantizer is set to be a value of 1, the quantizer is used for quantizing the signal output by the loop filtering module into a digital signal with 1 bit so as to reduce the nonlinearity of the feedback DAC; the first feedback circuit and the second feedback circuit are both used for converting a 1-bit digital signal output by the quantizer into an analog signal for feedback.

Description

Sigma-Delta analog-to-digital converter Technical Field The invention belongs to the technical field of analog-to-digital converters (ADC) and digital-to-analog (DAC), and particularly relates to a Sigma-Delta analog-to-digital converter. Background Sigma-Delta analog-to-digital converters, also known as Delta Sigma (DELTA SIGMA) analog-to-digital converters, mainly employ over-sampling techniques and noise shaping techniques in the processing of audio signals with high accuracy. The basic structure of a sigma-delta analog-to-digital converter comprises a loop filter, a quantizer and a feedback DAC, which together form a feedback loop. Typically, the Sigma-Delta analog-to-digital converter operates at a much higher rate than the bandwidth of the analog input signal to provide oversampling, the analog input is differentially (Delta) compared to the feedback signal (error signal), the difference signal resulting from this comparison is fed into the loop filter, and the Sigma-Delta analog-to-digital converter operates by feedback to bring this difference to zero. The quantizer adopted by the Sigma-Delta analog-to-digital converter can adopt a multi-bit quantizer, the result of the quantizer is directly and simultaneously output in multiple bits after being encoded, the signal-to-noise ratio can be increased by using the multi-bit quantizer, the Sigma-Delta analog-to-digital converter is easy to stabilize, fewer harmonic components are generated, but the multi-bit quantizer increases the complexity of the Sigma-Delta analog-to-digital converter and requires that the multi-bit DAC used for feedback have sufficient accuracy to ensure the accuracy and linearity of the final quantization of the quantizer. The multi-bit quantization requires a multi-bit feedback DAC, the non-linearity of the feedback DAC is caused by the mismatch of the unit structures of different feedback DACs, and the component matching index and accuracy requirements required by the feedback DAC increase with the increase of the number of bits of the feedback DAC, which increases the design complexity of the Sigma-Delta analog-to-digital converter. Disclosure of Invention In order to solve the technical problems, the invention discloses a Sigma-Delta analog-to-digital converter, in particular a Sigma-Delta analog-to-digital converter capable of realizing a time extension effect, which can reduce the design complexity of a DAC on a feedback loop, further reduce matching requirements and simultaneously ensure the linearity of the DAC. The following presents a simplified summary in order to provide a basic understanding of some aspects of the disclosed embodiments. This summary is not an extensive overview and is intended to neither identify key/critical elements nor delineate the scope of such embodiments. Its purpose is to present some concepts in a simplified form as a prelude to the more detailed description that is presented later. The Sigma-Delta analog-to-digital converter comprises a loop filter module, a first feedback circuit and a quantizer, wherein the loop filter module comprises summing nodes and integrators, the integrators are in cascade connection and exist in the loop filter module, the input end of each integrator is connected with the corresponding summing node to form a corresponding summing node of the integrator, the first feedback circuit is connected between the input end of the corresponding summing node of the integrator and the output end of the quantizer, and is used for performing first time extension processing on a quantized output signal output by the quantizer and converting the quantized output signal into a first feedback signal, and then the first feedback signal is transmitted to the input end of the corresponding summing node of the integrator. The Sigma-Delta analog-to-digital converter further comprises a second feedback circuit, wherein the second feedback circuit is connected between the summing node corresponding to the last-stage integrator and the output end of the quantizer, and is used for performing second time extension processing on the quantized output signal output by the quantizer and converting the quantized output signal into a second feedback signal, and then transmitting the second feedback signal to the summing node corresponding to the last-stage integrator, and the second time extension processing performed by the second feedback circuit is used for compensating the first time extension processing performed by the first feedback circuit. The quantizer, the second feedback circuit and the loop filter module are cascaded to form a compensation loop and form a second loop filter function, wherein the second loop filter function is used for compensating the first loop filter function so as to adjust the transmission function of the Sigma-Delta analog-to-digital converter to the original transmission function. The first feedback circuit further comprises a first feedback DAC and a first filter