CN-114303197-B - Read disturb scan combining

Abstract

A processing device in a memory system determines that data stored in a first block of a plurality of blocks of a memory component meets a first threshold criterion regarding a age of the data. In response to the data stored in the first block meeting the first threshold criteria, the processing device maintains a first counter to track a number of read operations performed on the first block. The processing device further determines that the data stored in the first block does not meet the first threshold criteria, and in response, maintains a second counter to track a number of read operations performed on a superblock comprising the plurality of blocks.

Inventors

• K.K. Mchirala
• 5. P. layapuru
• A. Marche
• H.R. hingidi
• G.S. Alsassoa

Assignees

• 美光科技公司

Dates

Publication Date

20260505

Application Date

20200731

Priority Date

20190802

Claims (20)

1. 1. A storage subsystem, comprising: a memory component comprising a plurality of blocks, and A processing device operatively coupled with the memory component to: Determining that data stored in a first block of the plurality of blocks of the memory component meets a first threshold criterion regarding a age of the data; Maintaining a first counter to track a number of read operations performed on the first block in response to the data stored in the first block meeting the first threshold criterion; Determining that the data stored in the first block does not meet the first threshold criterion, and In response to the data stored in the first block not meeting the first threshold criteria, a second counter is maintained to track a number of read operations performed on a superblock comprising the plurality of blocks.
2. 2. The storage subsystem of claim 1, wherein the processing device further performs the following operations: in response to the data stored in the first block meeting the first threshold criteria, a plurality of counters are maintained to track, respectively, a number of read operations performed on each of the plurality of blocks.
3. 3. The storage subsystem of claim 2, wherein the processing device further performs the following operations: setting the value of the second counter equal to the highest value of any one of the plurality of counters, and Discarding the plurality of counters.
4. 4. The storage subsystem of claim 1, wherein the plurality of blocks in the super block are arranged in stripes across a plurality of planes of the memory component.
5. 5. The storage subsystem of claim 1, wherein the processing device further performs the following operations: determining that the value of the first counter meets a second threshold criterion regarding the number of read operations performed on the first block, and In response to the value of the first counter meeting the second threshold criterion, a data integrity scan is performed to determine a first error rate of the first block.
6. 6. The storage subsystem of claim 5, wherein to perform the data integrity scan, the processing device: Determining whether the first error rate meets an error threshold criterion, and Responsive to the first error rate meeting the error threshold criterion: Repositioning data stored in the first block to another block on the memory component, and The value of the first counter is reset to an initial value.
7. 7. The storage subsystem of claim 1, wherein the processing device further performs the following operations: determining that the value of the second counter meets a third threshold criterion regarding the number of read operations performed on the superblock, and In response to the value of the second counter meeting the third threshold criterion, a data integrity scan is performed to determine an error rate for each of the plurality of blocks in the super block.
8. 8. The storage subsystem of claim 7, wherein to perform the data integrity scan, the processing device: Determining whether at least one of the error rates of at least one of the plurality of blocks meets an error threshold criterion, and Responsive to the at least one of the error rates meeting the error threshold criteria: Repositioning the data stored in the at least one of the plurality of blocks to another block on the memory component, and Resetting the value of the second counter to an initial value.
9. 9. The storage subsystem of claim 7, wherein to perform the data integrity scan, the processing device: determining whether a highest one of the error rates of corresponding ones of the plurality of blocks meets an error threshold criterion; In response to the highest one of the error rates meeting the error threshold criteria, determining whether a number of the error rates of corresponding ones of the plurality of blocks meeting the error threshold criteria meet a folding threshold criteria, and In response to the number meeting the fold threshold criterion: Repositioning the data stored in the corresponding one of the plurality of blocks to other blocks on the memory component, and Resetting the value of the second counter to an initial value.
10. 10. A method of operation of a memory subsystem, comprising: determining that data stored in a first block of a plurality of blocks of a memory component meets a first threshold criterion regarding a age of the data; in response to the data stored in the first block meeting the first threshold criteria, maintaining a first mode of operation of the memory subsystem, wherein in the first mode of operation, a read count for the first block is tracked at a physical block level; Determining that the data stored in the first block does not meet the first threshold criterion, and In response to the data stored in the first block not meeting the first threshold criteria, a second mode of operation of the memory subsystem is initiated, wherein in the second mode of operation the read count is tracked at a superblock level, wherein a superblock comprises the plurality of blocks.
11. 11. The method as recited in claim 10, further comprising: In the first mode of operation, determining that the read count meets a second threshold criterion regarding a number of read operations performed on the first block, and In response to the read count meeting the second threshold criterion, a data integrity scan is performed to determine a first error rate of the first block.
12. 12. The method of claim 11, wherein performing the data integrity scan comprises: Determining whether the first error rate meets an error threshold criterion, and Responsive to the first error rate meeting the error threshold criterion: Repositioning data stored in the first block to another block on the memory component, and The read count of the first block is reset to an initial value.
13. 13. The method as recited in claim 10, further comprising: In the second mode of operation, determining that the read count meets a third threshold criterion regarding a number of read operations performed on the superblock, and In response to the read count meeting the third threshold criterion, a data integrity scan is performed to determine an error rate for each of the plurality of blocks in the super block.
14. 14. The method of claim 13, wherein performing the data integrity scan comprises: Determining whether at least one of the error rates of at least one of the plurality of blocks meets an error threshold criterion, and Responsive to the at least one of the error rates meeting the error threshold criteria: Repositioning the data stored in the at least one of the plurality of blocks to another block on the memory component, and The read count for the superblock is reset to an initial value.
15. 15. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to: determining that data stored in a first block of a plurality of blocks of a memory component meets a first threshold criterion regarding a age of the data; Maintaining a first counter to track a number of read operations performed on the first block in response to the data stored in the first block meeting the first threshold criterion; Determining that the data stored in the first block does not meet the first threshold criterion, and In response to the data stored in the first block not meeting the first threshold criteria, a second counter is maintained to track a number of read operations performed on a superblock comprising the plurality of blocks.
16. 16. The non-transitory computer-readable storage medium of claim 15, wherein the instructions further cause the processing device to: in response to the data stored in the first block meeting the first threshold criteria, a plurality of counters are maintained to track, respectively, a number of read operations performed on each of the plurality of blocks.
17. 17. The non-transitory computer-readable storage medium of claim 16, wherein the instructions further cause the processing device to: setting the value of the second counter equal to the highest value of any one of the plurality of counters, and Discarding the plurality of counters.
18. 18. The non-transitory computer-readable storage medium of claim 15, wherein the instructions further cause the processing device to: determining that the value of the first counter meets a second threshold criterion regarding the number of read operations performed on the first block, and In response to the value of the first counter meeting the second threshold criterion, performing a data integrity scan to determine a first error rate of the first block, wherein to perform the data integrity scan, the processing device: Determining whether the first error rate meets an error threshold criterion, and Responsive to the first error rate meeting the error threshold criterion: Repositioning data stored in the first block to another block on the memory component, and The value of the first counter is reset to an initial value.
19. 19. The non-transitory computer-readable storage medium of claim 15, wherein the instructions further cause the processing device to: determining that the value of the second counter meets a third threshold criterion regarding the number of read operations performed on the superblock, and In response to the value of the second counter meeting the third threshold criterion, performing a data integrity scan to determine an error rate for each of the plurality of blocks in the super block, wherein to perform the data integrity scan, the processing device: Determining whether at least one of the error rates of at least one of the plurality of blocks meets an error threshold criterion, and Responsive to the at least one of the error rates meeting the error threshold criteria: Repositioning the data stored in the at least one of the plurality of blocks to another block on the memory component, and Resetting the value of the second counter to an initial value.
20. 20. The non-transitory computer-readable storage medium of claim 19, wherein to perform the data integrity scan, the instructions further cause the processing device to: determining whether a highest one of the error rates of corresponding ones of the plurality of blocks meets an error threshold criterion; In response to the highest one of the error rates meeting the error threshold criteria, determining whether a number of the error rates of corresponding ones of the plurality of blocks meeting the error threshold criteria meet a folding threshold criteria, and In response to the number meeting the fold threshold criterion: Repositioning the data stored in the corresponding one of the plurality of blocks to other blocks on the memory component, and Resetting the value of the second counter to an initial value.

Description

Read disturb scan combining Technical Field Embodiments of the present disclosure relate generally to memory subsystems and, more particularly, to managing memory subsystems that include memory components having different characteristics. Background The memory subsystem may be a storage system, a memory module, or a hybrid of storage and memory modules. The memory subsystem may include one or more memory components that store data. For example, the memory components may be non-volatile memory components and volatile memory components. In general, a host system may utilize a memory subsystem to store data at and retrieve data from a memory component. Drawings The present disclosure will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the disclosure. FIG. 1 illustrates an example computing environment including a memory subsystem, according to some embodiments of the disclosure. Fig. 2 is a flowchart of an example method of using a read counter with hierarchical granularity, according to some embodiments of the present disclosure. FIG. 3 is a block diagram illustrating a read counter at physical block level and superblock level granularity, according to some embodiments of the present disclosure. FIG. 4 is a flowchart of an example method of triggering a data integrity scan using a read counter at a physical block level granularity, according to some embodiments of the present disclosure. FIG. 5 is a flowchart of an example method of triggering a data integrity scan using a read counter at superblock level granularity, according to some embodiments of the present disclosure. Fig. 6 is a flowchart of an example method of determining a read count scale factor, according to some embodiments of the present disclosure. Fig. 7 is a block diagram illustrating a data structure for storing a read count scale factor according to some embodiments of the present disclosure. Fig. 8 is a flowchart of an example method of using a read count scaling factor in incrementing a read counter to trigger a data integrity scan, according to some embodiments of the present disclosure. Fig. 9 is a flowchart of an example method for using layering criteria for block refresh after a data integrity scan, according to some embodiments of the present disclosure. FIG. 10 is a block diagram of an example computer system in which embodiments of the present disclosure may operate. Detailed Description Aspects of the present disclosure relate to read disturb scan combining across multiple planes of memory components to minimize system bandwidth loss in a memory subsystem. The memory subsystem may be a memory device, a memory module, or a hybrid of memory devices and memory modules. Examples of memory devices and memory modules are described below in connection with FIG. 1. In general, a host system may utilize a memory subsystem that includes one or more memory components. The host system may provide data to be stored at the storage subsystem and may request data to be retrieved from the storage subsystem. The memory component may be a memory device, such as a non-volatile memory device. A nonvolatile memory device is a package of one or more dies. Each die may be comprised of one or more planes. For some types of non-volatile memory devices (e.g., NAND devices), each plane is made up of a set of physical blocks. For some memory devices, a block is the smallest area that is erasable. Each block is made up of a set of pages. Each page is made up of a set of memory cells that store bits of data. When data is written to a memory cell of a memory component for storage, the memory cell may degrade. Thus, each memory cell of the memory component may handle a limited number of write operations performed before the memory cell is no longer able to reliably store data. Data stored at the memory cells of the memory component may be read from the memory component and transferred to the host system. When reading data from memory cells of a memory component, nearby or adjacent memory cells may experience so-called read disturb. Read disturb is the result of a continuous read from one memory cell without intervening erase operations, which causes other nearby memory cells to change over time (e.g., become programmed). If too many read operations are performed on the memory cells, data stored at adjacent memory cells of the memory component may be corrupted or incorrectly stored at the memory cells. This may result in a higher data error rate of the data stored at the memory cells. This may increase the use of error detection and correction operations (e.g., error control operations) for subsequent operations (e.g., reads and/or writes) performed on the memory cells. Increased use of error control operations may result in reduced performance of conventional memory subsystems. In addition, as the error rate of memory cells or blocks continues to increase, it may even exceed the err