CN-114333936-B - Nonvolatile magnetic random access memory structure and nonvolatile magnetic random access memory

CN114333936BCN 114333936 BCN114333936 BCN 114333936BCN-114333936-B

Abstract

The invention discloses a nonvolatile magnetic random access memory structure and a nonvolatile magnetic random access memory, wherein the memory structure comprises at least one memory unit, the memory unit comprises a first memory bank, a second memory bank and a switch transistor, and the magnetization states of the first memory bank and the second memory bank are opposite. The first end of the first memory bank and the first end of the second memory bank are respectively connected with the drain electrode of the switching transistor. The second end of the first memory bank is connected with the first bit line, and the second end of the second memory bank is connected with the second bit line and is respectively connected to the reading circuit. The grid electrode of the switching transistor is connected with the word line, the source electrode of the switching transistor is connected with the source line, and the source line is connected with the first voltage generator. According to the scheme, two memory banks with opposite magnetization states are connected in parallel, the characteristic that the area occupied ratio of the memory banks is small is utilized, when one memory bank is used as a judging unit, the other memory bank is used as a reference unit, so that the influence of drift current on single reference current is avoided, and the judging sensitivity is improved.

Inventors

WANG TAO
Wang Tengye
LUO RUIMING

Assignees

中芯国际集成电路制造(上海)有限公司
中芯国际集成电路制造(北京)有限公司

Dates

Publication Date: 20260508
Application Date: 20200930

Claims (12)

1. A non-volatile magnetic random access memory, the non-volatile memory comprising a non-volatile magnetic random access memory structure, and a read circuit, characterized in that, The nonvolatile memory structure comprises at least one memory unit, wherein the memory unit comprises a first memory bank, a second memory bank and a switch transistor, and the magnetization states of the first memory bank and the second memory bank are opposite; the first end of the first memory bank and the first end of the second memory bank are respectively connected with the drain electrode of the same switching transistor; the second end of the first memory bank is connected with the first bit line, and the second end of the second memory bank is connected with the second bit line and respectively connected to the reading circuit; the gate of the switch transistor is connected with a word line, the source of the switch transistor is connected with a source line, and the source line is connected with a first voltage generator, and The read circuit includes: A comparison amplifier; A bit line address selector including a first bit line address selector and a second bit line address selector, wherein The first bit line address selector is connected with the non-inverting input end of the comparison amplifier and the second end of the first memory bank, the second bit line address selector is connected with the inverting input end of the comparison amplifier and the second end of the second memory bank, and The non-inverting input ends of the first bit line address selector and the comparison amplifier are connected to a data voltage, and the inverting input ends of the second bit line address selector and the comparison amplifier are connected to a reference voltage; the reading circuit also comprises a first bias voltage module, a second bias voltage module and a bias current module, The first bias voltage module is connected with the data voltage, the second bias voltage module is connected with the reference voltage, and The first bias voltage module and the second bias voltage module are also connected to a power supply voltage, and the bias current module is located between the first bias voltage module and the second bias voltage module.
2. The non-volatile magnetic random access memory of claim 1, wherein the first memory bank and the second memory bank are both magnetic tunnel junctions, and the first terminal is a fixed layer and the second terminal is a free layer.
3. The non-volatile magnetic random access memory of claim 1 or 2, wherein the non-volatile memory structure comprises an array of memory cells comprising a plurality of the memory cells, wherein, In the memory cell array, the gate of the switch transistor in the memory cells of each row is connected to the word line of each row, and The source of the switch transistor in each column of memory cells is connected to the source line of each column, and In the memory cell array, a first end of the memory bank in the memory cells of each column is connected to the bit line of each column.
4. The non-volatile magnetic random access memory of claim 1 or 2, wherein the switching transistor is an NMOS transistor.
5. The nonvolatile magnetic random access memory according to claim 1, wherein a first bit line voltage clamp is further provided between said first bit line address selector and said non-inverting input of said comparison amplifier, and A second bit line voltage clamp is also provided between the second bit line address selector and the inverting input of the comparison amplifier.
6. The nonvolatile magnetic random access memory according to claim 1, wherein the read circuit further comprises a second voltage generator and a third voltage generator, wherein, The second voltage generator is connected with the first bit line address selector to provide voltage for the write operation of the first memory bank, and The third voltage generator is connected to the second bit line address selector to provide a voltage for a write operation of the second bank.
7. The non-volatile magnetic random access memory of claim 6, wherein the second voltage generator and the third voltage generator are the same voltage generator.
8. The non-volatile magnetic random access memory of claim 1, wherein the bias current module comprises a first bias current circuit and a second bias current circuit, the first bias current circuit and the second bias current circuit being mirror symmetric, and the first bias current circuit and the second bias current circuit being connected in parallel with the supply voltage.
9. The nonvolatile magnetic random access memory according to claim 8, wherein said first bias current circuit includes a first diode, a first capacitor and a second capacitor, said first diode being connected in parallel with said first capacitor and in series with said second capacitor, and The second bias current circuit comprises a second diode, a third capacitor and a fourth capacitor, wherein the second diode is connected with the third capacitor in parallel and then connected with the fourth capacitor in series, and The first bias current circuit is connected with the reference voltage and the second bit line voltage clamp, and the second bias current circuit is connected with the data voltage and the first bit line voltage clamp.
10. The nonvolatile magnetic random access memory according to claim 1, wherein the first bias voltage module includes a first transistor and a second transistor connected in series, wherein The first transistor is connected to the power supply voltage, the second transistor is connected to the first bit line voltage clamp, the first transistor and the second transistor are opposite in polarity, and The second bias voltage module comprises a third transistor and a fourth transistor connected in series, wherein The third transistor is connected with the power supply voltage, the fourth transistor is connected with the second bit line voltage clamp, and the polarities of the third transistor and the fourth transistor are opposite.
11. The nonvolatile magnetic random access memory according to claim 10, wherein said bias current module includes a precharge circuit, and first, second, third, and fourth switching elements connected to said precharge circuit, wherein, The first switching element is connected with the drains of the first transistor and the third transistor, and the sources of the second transistor and the fourth transistor; The two switching elements are connected with the gates of the first transistor, the second transistor, the third transistor and the fourth transistor; The third switching element is connected with the drain electrode of the second transistor; The fourth switching element is connected to the drain of the fourth transistor.
12. The nonvolatile magnetic random access memory according to claim 11, wherein the first transistor and the third transistor are PMOS transistors, and The second transistor and the fourth transistor are NMOS transistors.

Description

Nonvolatile magnetic random access memory structure and nonvolatile magnetic random access memory Technical Field The present invention relates to the field of semiconductor technology, and in particular, to a nonvolatile magnetic random access memory structure and a nonvolatile magnetic random access memory. Background A magnetic random access memory (MRAM, magnetic Random Access Memory) is a Non-Volatile (Non-Volatile) magnetic random access memory. It has high-speed read-write capability of Static Random Access Memory (SRAM), and high integration of Dynamic Random Access Memory (DRAM), and is a potential memory type in the trend of shrinking semiconductor device process nodes. The prior art nonvolatile magnetic random access memory structure is generally composed of a magnetic tunnel junction (MTJ, magnetic tunnel junction) and a transistor, i.e., a structure in which one magnetic tunnel junction is matched with one transistor. Specifically, as shown in fig. 1a, the memory cell of the nonvolatile magnetic random access memory includes memory banks 02, and a tertiary transistor 05 connected to each memory bank 02. Where m=1 means that the bias voltage circuit corresponds to one memory bank 02, and m=2 means that the bias voltage circuit corresponds to two memory banks 02. Each bank 02 is connected to its corresponding bit line address selector 03 and bit line voltage clamp 04, respectively, and then to the non-inverting input or inverting input of the comparison amplifier 01. The gate of the triode 05 is connected to a Word Line (WL) of the chip for gating the MRAM memory cell, and the MTJ and the triode 05 are connected in series to a Bit Line (BL) of the chip for performing read/write operations. And when a plurality of MRAM memory cells form a memory cell array, the word line of each MRAM memory cell extends along a row of memory cells and the bit line extends along a column of memory cells, each MRAM memory cell being located at an intersection of the word line and the bit line. Referring to fig. 2, in the prior art, a plurality of memory cells of a nonvolatile magnetic random access memory may be formed into a memory cell array. The gate G of the corresponding tertiary transistor 05 of each row of memory banks 02 is connected to the word line WL of each row, the source S of the corresponding tertiary transistor 05 of each column of memory banks 02 is connected to the source line SL of each column, and one end of each column of memory banks 02 is connected to the bit line BL of each column. The memory cells store information using magnetization directions, and the magnetization of each memory cell exhibits one of two stable directions, namely, parallel and anti-parallel directions, i.e., logic variables "0" and "1". The magnetization direction affects the resistance of the memory cell, R if the magnetization direction is parallel and R+ [ delta ] R if the magnetization direction is antiparallel. The logic state of the memory cell can be read out through the resistance of the memory cell. The MRAM is specifically read by applying a voltage to the word line across a selected memory cell while reading the current on the bit line to read the resistance state of the memory cell. The sense current (Is) Is the ratio of the sense voltage (Vs) to the resistance of the selected memory cell. The sense current may be converted to a voltage and the resistance state of the selected memory cell may be determined by comparing the data voltage (Vdata) with a reference voltage (Vref). When Vdata > Vref, the logic value of the selected memory cell is "0", and when Vdata < Vref, the logic value is "1". The existing MRAM memory cell is limited by the device volume and the process, and the ratio of the resistance values is lower in a high-resistance state and a low-resistance state, so that the window for distinguishing the two states of the sense amplifier is smaller, and the judgment margin is smaller. This causes a problem of slow reading speed. In particular, in a memory cell array including a plurality of memory cells, a fixed reference cell is used as a comparison standard, and the accuracy of judgment is affected by the influence of drift current on the memory cells. In the conventional sense amplifier, the reference resistor is an average value of the high-resistance state and the low-resistance state, and the overall judgment margin depends on the smaller gap current (the difference between the smaller one of the low-resistance state and the high-resistance state and the reference current), that is, only the smaller gap current is used for judging the resistance state, and the other part is lost. Selecting the appropriate reference cell can increase the reference resistance of the high and low resistance states, but if a larger judgment margin is to be obtained, the read time still needs to be increased. Thus, there is a need to provide a memory cell that can improve the judgment margin when judging the high-low r