CN-114334977-B - Semiconductor device and manufacturing method thereof

CN114334977BCN 114334977 BCN114334977 BCN 114334977BCN-114334977-B

Abstract

The present invention provides a semiconductor device and a method of manufacturing the same, the semiconductor device includes a substrate, a first insulating stack laminated on the substrate, and a second insulating stack laminated on the first insulating stack. A first contact hole is formed in the first insulating lamination, a stacking contact plug is filled in the first contact hole from bottom to top, and the stacking contact plug does not fill the first contact hole. A second contact hole communicating with the first contact hole is formed in the second insulating stack. The lower electrode also extends downwards into the second contact hole and the first contact hole in sequence to be in contact with the stacking contact plug. The lower electrode formed above the two insulating laminates is further extended downwards into the first contact hole and the second contact hole to be in contact with the reserved stacking contact plug, so that part of the lower electrode in contact with the stacking contact plug forms an anchor-like structure, the whole lower electrode is supported, and the whole lower electrode is prevented from tilting. The surface area of the lower electrode is increased, the capacitor capacitance is improved.

Inventors

GUO BINGRONG
YANG TAO
HU YANPENG
LU YIHONG

Assignees

中国科学院微电子研究所
中国科学院微电子研究所
真芯(北京)半导体有限责任公司
真芯(北京)半导体有限责任公司

Dates

Publication Date: 20260421
Application Date: 20201010
Priority Date: 20201010

Claims (8)

1. A semiconductor device, comprising: A substrate comprising a transistor and a bit line structure, the bit line structure being formed over the transistor; The semiconductor device comprises a substrate, a first insulating lamination layer, a second insulating lamination layer, a first contact hole, a second contact hole, a first insulating layer, a second insulating layer, a first insulating layer and a second insulating layer, wherein the first contact hole is formed in the first insulating lamination layer; A second insulating layer stack stacked on the first insulating layer stack, wherein a second contact hole communicated with the first contact hole is formed in the second insulating layer stack; a lower electrode formed above the second insulating stack, and extending downward into the second contact hole and the first contact hole in sequence to contact the stacked contact plug; The height of the stacking contact plug is h1, and the height of the first contact hole is h2, wherein h2 is more than or equal to 20% and less than or equal to 80% of h2.
2. The semiconductor device according to claim 1, wherein the lower electrode extending to a wall of the second contact hole and the first contact hole is deposited on the walls of the first contact hole and the second contact hole; The lower electrode extending to the upper end face of the stacking contact plug is deposited on the upper end face of the stacking contact plug.
3. The semiconductor device according to claim 1, wherein the lower electrode has a cylindrical shape, wherein a bottom wall of the lower electrode is deposited on an upper end surface of the stacked contact plug, and wherein side walls of the lower electrode are partially deposited on walls of the first contact hole and the second contact hole and partially exposed outside the first contact hole and the second contact hole.
4. The semiconductor device according to claim 1, wherein an upper electrode and a dielectric layer for insulating and isolating the lower electrode from the upper electrode are formed on each of a bottom wall, an inner side wall, and an outer side wall of the lower electrode exposed to the outer portions of the first contact hole and the second contact hole.
5. A method of manufacturing a semiconductor device, comprising: Providing a substrate comprising a transistor and a bit line structure, the bit line structure being formed over the transistor; laminating an insulating layer on the substrate; forming a contact hole in the insulating layer; The contact hole is filled with a stacking contact plug and a landing pad electrically connected with the stacking contact plug, and the stacking contact plug is in contact with a source region or a drain region of the transistor; the insulating layer comprises a first insulating lamination layer, an insulating part for isolating two adjacent stacked contact plugs is further formed in the first insulating lamination layer, and the stacked contact plugs and the insulating part are formed between adjacent bit line structures; laminating a sacrificial film layer on the insulating layer; Forming a capacitor hole communicated with the landing pad in the sacrificial film layer; Removing the landing pad; removing part of the stacking contact plugs from top to bottom; forming a lower electrode above the insulating layer, wherein the lower electrode also extends downwards into the contact hole to be in contact with the reserved part of the stacking contact plug; The landing pad filled with the stacked contact plugs and electrically connected with the stacked contact plugs in the contact holes is specifically: filling stacked contact plugs in the contact holes; filling a conductor film in contact with the stacking contact plug in the contact hole; Filling landing pads in contact with the conductor film in the contact holes; after the removing the landing pad, the manufacturing method further includes removing the conductor film before removing a portion of the stacked contact plugs from top to bottom.
6. The method of manufacturing as claimed in claim 5, wherein removing the landing pad, the conductive film and a portion of the stacked contact plugs is performed by removing the landing pad, the conductive film and a portion of the stacked contact plugs in the contact holes from top to bottom using a wet etching or a remote plasma dry cleaning process.
7. The method of manufacturing of claim 5, wherein forming a lower electrode over the insulating layer, and wherein the lower electrode extends down into the contact hole to contact a remaining portion of the stacked contact plug comprises: and forming lower electrodes which are contacted with the reserved stacking contact plugs on the hole walls of the capacitor holes and the contact holes and the upper end surfaces of the reserved portions of the stacking contact plugs.
8. The method of manufacturing as claimed in claim 7, wherein forming the lower electrode in contact with the remaining stacked contact plug on the walls of the capacitor hole and the contact hole and the remaining portion of the upper end surface of the stacked contact plug comprises: depositing a lower electrode material layer on the surface of the sacrificial film layer, the hole walls of the capacitor holes and the contact holes and the upper end surfaces of the reserved parts of the stacking contact plugs; And removing the lower electrode material layer on the surface of the sacrificial film layer to form a lower electrode contacted with the reserved stacking contact plug.

Description

Semiconductor device and manufacturing method thereof Technical Field The present invention relates to the field of semiconductor manufacturing technology, and in particular, to a semiconductor device and a method for manufacturing the same. Background A Capacitor (Capacitor) is an element that can store electric power and electric energy. Different amounts of charge can be stored in the capacitor by applying different voltages across the two electrodes of the capacitor. On this basis, the storage of different data can be realized by a capacitor. It follows that the quality of the capacitor directly affects the data storage performance of the semiconductor device. In order to improve the driving performance of the memory, it is necessary to increase the capacitance of the capacitor. The general way to increase the capacitance of the capacitor is to increase the height of the capacitor. However, the height of the capacitor increases, resulting in an increase in the Aspect Ratio (Aspect Ratio) of the capacitor. The aspect ratio of the capacitor increases, so that problems such as tilting, bending and even collapsing of the capacitor occur easily when the Wet Clean process is performed. Disclosure of Invention The invention provides a semiconductor device and a method for manufacturing the same, which can effectively improve the charge storage capacity of a capacitor and can effectively prevent the capacitor from tilting, bending or collapsing. In a first aspect, the present invention provides a semiconductor device comprising a substrate, a first insulating stack laminated on the substrate, and a second insulating stack laminated on the first insulating stack. The first insulating lamination is provided with a first contact hole, a stacking contact plug is filled in the first contact hole from bottom to top, and the stacking contact plug does not fill the first contact hole. A second contact hole is formed in the second insulating stack in communication with the first contact hole. The semiconductor device further includes a lower electrode formed over the second insulating stack, and the lower electrode further extends down into the second contact hole and the first contact hole in sequence to contact the stacked contact plug. In the above-mentioned scheme, by removing the conductor film in the second contact hole and the landing pad (LANDING PAD, abbreviated as LP) in contact with the conductor film, and also removing part of the stacking contact plug (Buried Contact, abbreviated as BC) in the first contact hole, the lower electrode formed above the two insulating stacks is further extended downward into the first contact hole and the second contact hole to contact with the remaining stacking contact plug, so that the part of the lower electrode in contact with the stacking contact plug forms an anchor-like structure, the whole lower electrode can be supported, and the whole lower electrode is prevented from tilting. When a dielectric layer and an upper electrode are deposited on the lower electrode in the subsequent process, the structural part similar to an anchor in the lower electrode can also prevent the whole lower electrode from bending and deforming, thereby preventing the capacitor from collapsing. And the surface area of the lower electrode can be increased by the part of the lower electrode extending into the first contact hole and the second contact hole, so that the charge storage capacity of the capacitor is improved, the capacitance of the capacitor is improved, and the storage performance is improved. And the lower electrode is extended downwards to the first contact hole and the second contact hole to be directly contacted with the reserved stacking contact plug, so that the contact number between different layers is reduced and the resistance of interlayer current transmission is reduced by replacing the contact mode of the lower electrode with the stacking contact plug through a landing pad and a conductor film. When the capacitor is applied, the structural part similar to an anchor in the lower electrode supports the whole lower electrode, so that the capacitor structure is firm, the height-width ratio of the stacked capacitor can be properly increased, the capacitance of the capacitor is increased, and the storage performance is further improved. In a specific embodiment, the lower electrode extending to the walls of the second contact hole and the first contact hole is deposited on the walls of the first contact hole and the second contact hole, and the lower electrode extending to the upper end surface of the stacking contact plug is deposited on the upper end surface of the stacking contact plug, so that the contact strength between the lower electrode and the walls of the contact holes and the stacking contact plug is improved, and the supporting effect of the whole lower electrode is improved. In a specific embodiment, the lower electrode is formed in a cylindrical shape, wherein t