CN-114337618-B - Comparator and analog-to-digital converter based on pre-amplification stage structure

CN114337618BCN 114337618 BCN114337618 BCN 114337618BCN-114337618-B

Abstract

The invention is suitable for the technical field of integrated circuits, and provides a comparator and an analog-to-digital converter based on a pre-amplification stage structure, wherein the comparator comprises a first pre-amplification stage, a second pre-amplification stage and a first output stage, wherein the input end of the first pre-amplification stage is connected with a differential input signal, amplifies and outputs the differential input signal, and outputs a first differential output signal; the input end of the second pre-amplification stage is connected with the first differential output signal, the first differential output signal is amplified and output, the second differential output signal is output, a positive feedback unit is arranged between the output end of the second pre-amplification stage and the input end of the second pre-amplification stage, the voltage gain of the second pre-amplification stage is improved through the positive feedback unit, the input end of the latch is connected with the second differential output signal, the voltage gain of the second pre-amplification stage is improved through the positive feedback unit, particularly the voltage gain of a small signal is improved, and then equivalent input noise of the comparator can be effectively reduced.

Inventors

XU DAIGUO
GAO WEIQI
JIANG HEQUAN
LI RUZHANG
WANG JIANAN
FU DONGBING
CHEN GUANGBING
YU ZHOU
ZHANG ZHENGPING
ZHU CAN

Assignees

重庆吉芯科技有限公司
重庆吉芯科技有限公司

Dates

Publication Date: 20260421
Application Date: 20211222
Priority Date: 20211222

Claims (8)

1. A comparator based on a pre-amplification stage structure, comprising at least: The input end of the first pre-amplification stage is connected with a differential input signal, and the differential input signal is amplified and output to output a first differential output signal; the input end of the second pre-amplification stage is connected with the first differential output signal, the first differential output signal is amplified and output, the second differential output signal is output, a positive feedback unit is arranged between the output end and the input end of the second pre-amplification stage, and the voltage gain of the second pre-amplification stage is improved through the positive feedback unit; a latch having an input terminal coupled to the second differential output signal; The first pre-amplification stage comprises; the first NMOS tube, the second NMOS tube, the third NMOS tube, the first PMOS tube and the second PMOS tube; The source electrode of the first NMOS tube is grounded, the grid electrode of the first NMOS tube is connected with a first control signal, and the drain electrode of the first NMOS tube is connected with a first node; The source electrode of the second NMOS tube is connected with the first node, the grid electrode of the second NMOS tube is connected with the differential input signal, and the drain electrode of the second NMOS tube is connected with the second node; The source electrode of the third NMOS tube is connected with the first node, the grid electrode of the third NMOS tube is connected with the differential input signal, and the drain electrode of the third NMOS tube is connected with the third node; The drain electrode of the first PMOS tube is connected with the second node, and the grid electrode of the first PMOS tube is connected with the first control signal The source electrode of the first PMOS tube is connected with the working voltage; The drain electrode of the second PMOS tube is connected with the third node, and the grid electrode of the second PMOS tube is connected with the first control signal The source electrode of the second PMOS tube is connected with the working voltage; the first differential output signal is output through the second node and the third node; the second pre-amplification stage includes a pre-amplification stage main body unit and the positive feedback unit, and the positive feedback unit includes: A fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube and a seventh NMOS tube; The grid electrode of the fourth NMOS tube is connected with a fourth node, the source electrode of the fourth NMOS tube is connected with a fifth node, and the drain electrode of the fourth NMOS tube is connected with the grid electrode of the seventh NMOS tube; the source electrode of the fifth NMOS tube is connected with the fifth node, the grid electrode of the fifth NMOS tube is connected with the sixth node, and the drain electrode of the fifth NMOS tube is connected with the grid electrode of the sixth NMOS tube; the source electrode of the sixth NMOS tube is connected with the sixth node, and the drain electrode of the sixth NMOS tube is connected with the seventh node; and the source electrode of the seventh NMOS tube is connected with the fourth node, and the drain electrode of the seventh NMOS tube is connected with the eighth node.
2. The pre-amp stage structure based comparator of claim 1, further comprising 1 pre-amp stage, the pre-amp stage being serially connected between the first pre-amp stage and the second pre-amp stage.
3. The comparator based on a pre-amplification stage structure according to claim 1, further comprising N pre-amplification stages, N being an integer greater than or equal to 2, the N pre-amplification stages being cascade-arranged and serially connected between the first pre-amplification stage and the second pre-amplification stage.
4. A comparator based on a pre-amp stage structure according to claim 3, characterized in that the structure of N pre-amp stages is identical to the structure of the second pre-amp stage.
5. The comparator based on a pre-amplification stage structure according to claim 1, wherein the pre-amplification stage body unit comprises: an eighth NMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube and a sixth PMOS tube; the source electrode of the eighth NMOS tube is grounded, and the drain electrode of the eighth NMOS tube is connected with the fifth node; The second control signal is respectively connected with the grid electrode of the eighth NMOS tube, the grid electrode of the third PMOS tube, the grid electrode of the fourth PMOS tube, the grid electrode of the fifth PMOS tube and the grid electrode of the sixth PMOS tube, and the working voltage is respectively connected with the source electrode of the third PMOS tube, the source electrode of the fourth PMOS tube, the source electrode of the fifth PMOS tube and the source electrode of the sixth PMOS tube; the drain electrode of the third PMOS tube is connected with the eighth node, the drain electrode of the fourth PMOS tube is connected with the seventh node, the drain electrode of the fifth PMOS tube is connected with the drain electrode of the fourth NMOS tube, and the drain electrode of the sixth PMOS tube is connected with the drain electrode of the fifth NMOS tube; the first differential output signal is respectively connected with the fourth node and the sixth node, and the second differential output signal is output through the seventh node and the eighth node.
6. The comparator based on a pre-amplification stage structure according to claim 5, wherein the latch comprises a sampling unit and a holding unit; The input end of the sampling unit is respectively connected with the sixth node and the eighth node, and the sampling unit samples the second differential output signal; the output end of the sampling unit is connected with the holding unit, and the holding unit holds the second differential output signal.
7. The comparator based on a pre-amp stage structure of claim 5, wherein the first control signal and the second control signal are the same control signal.
8. An analog-to-digital converter, characterized in that it comprises a comparator based on a pre-amplifier stage structure according to any of claims 1-7.

Description

Comparator and analog-to-digital converter based on pre-amplification stage structure Technical Field The present invention relates to the field of integrated circuits, and in particular, to a comparator and an analog-to-digital converter based on a pre-amplification stage structure. Background In recent years, with the development of integrated circuit manufacturing technology, feature sizes of CMOS devices have been reduced, and operating voltages of integrated circuits have been reduced. Under the deep submicron process, the working speed of the analog-to-digital converter is greatly improved, and meanwhile, the power consumption is further reduced. But as a core component of the analog-to-digital converter, the performance of the comparator becomes a bottleneck for high-speed low-power design. Conventional comparator structures are difficult to meet the requirements of speed, power consumption, low power supply voltage and the like. In the occasion of lower precision requirement, can adopt the single-stage latch structure as the comparator structure, the advantage of this structure of single-stage latch is fast, the low power consumption, but the shortcoming is noise and offset are great. In the occasion of high precision requirement, in order to suppress the defects of high noise and high offset of a single-stage latch structure, a comparator is usually connected with a latch stage after cascade connection of a plurality of stages of pre-amplification stages. However, the disadvantage of adopting a structure of cascade connection of the multi-stage pre-amplification stage and the latch stage is that the reset speed of the comparator can be obviously reduced and the power consumption of the comparator can be increased due to the existence of the capacitor at the output end of the pre-amplification stage in the reset process of the comparator. Disclosure of Invention The invention provides a comparator and an analog-to-digital converter based on a pre-amplification stage structure, which are used for solving the problem of large noise of the comparator in the prior art. To achieve the above and other related objects, the present invention provides a comparator based on a pre-amplification stage structure, comprising: The input end of the first pre-amplification stage is connected with a differential input signal, and the differential input signal is amplified and output to output a first differential output signal; the input end of the second pre-amplification stage is connected with the first differential output signal, the first differential output signal is amplified and output, the second differential output signal is output, a positive feedback unit is arranged between the output end and the input end of the second pre-amplification stage, and the voltage gain of the second pre-amplification stage is improved through the positive feedback unit; And the input end of the latch is connected with the second differential output signal. Optionally, the comparator based on the pre-amplification stage structure further comprises 1 pre-amplification stage, and the pre-amplification stage is connected in series between the first pre-amplification stage and the second pre-amplification stage. Optionally, the comparator based on the pre-amplification stage structure further includes N pre-amplification stages, N is an integer greater than or equal to 2, and N pre-amplification stages are cascade-arranged and then serially connected between the first pre-amplification stage and the second pre-amplification stage. Optionally, the structure of the N pre-amplifying stages is the same as the structure of the second pre-amplifying stage. Optionally, the first pre-amplification stage includes; the first NMOS tube, the second NMOS tube, the third NMOS tube, the first PMOS tube and the second PMOS tube; The source electrode of the first NMOS tube is grounded, the grid electrode of the first NMOS tube is connected with a first control signal, and the drain electrode of the first NMOS tube is connected with a first node; The source electrode of the second NMOS tube is connected with the first node, the grid electrode of the second NMOS tube is connected with the differential input signal, and the drain electrode of the second NMOS tube is connected with the second node; The source electrode of the third NMOS tube is connected with the first node, the grid electrode of the third NMOS tube is connected with the differential input signal, and the drain electrode of the third NMOS tube is connected with the third node; the drain electrode of the first PMOS tube is connected with the second node, the grid electrode of the first PMOS tube is connected with the first control signal, and the source electrode of the first PMOS tube is connected with the working voltage; the drain electrode of the second PMOS tube is connected with the third node, the grid electrode of the second PMOS tube is connected with the first control signal