CN-114337659-B - Digital phase-locked loop circuit

Abstract

There is provided a digital phase-locked loop circuit including a synchronization control module configured to generate an input characterization signal characterizing a periodic variation of an input periodic signal with respect to a base clock signal based on the base clock signal and the input periodic signal, a count control module configured to generate a clock count result characterizing a multiple relationship between the period of the input characterization signal and the period of the base clock signal based on the base clock signal and the input characterization signal, an operation control module configured to generate a base clock control variable based on a preset frequency multiplication coefficient between a frequency of an output clock signal and a frequency of the input periodic signal and to generate an output clock control variable based on the clock count result, and an output control module configured to generate an output control signal based on the base clock control variable and the output clock control variable and to generate the output clock signal based on the output control signal and the base clock signal.

Inventors

• LIU TUOFU
• LI MENG

Assignees

• 昂宝集成电路股份有限公司
• 昂宝电子（上海）有限公司

Dates

Publication Date

20260421

Application Date

20211223

Priority Date

20211223

Claims (18)

1. 1. A digital phase locked loop circuit comprising: A synchronization control module configured to generate an input characterization signal that characterizes a periodic variation of the input periodic signal relative to a base clock signal based on the base clock signal and the input periodic signal; A count control module configured to generate a clock count result characterizing a multiple relationship between a period of the input characterization signal and a period of the base clock signal based on the base clock signal and the input characterization signal; An operation control module configured to generate a basic clock control variable based on a preset frequency multiplication coefficient between a frequency of an output clock signal and a frequency of the input periodic signal, and to generate an output clock control variable based on the clock count result, and An output control module configured to generate an output control signal based on the base clock control variable and the output clock control variable, and to generate the output clock signal based on the output control signal and the base clock signal, wherein The counting control module and the operation control module take rising edges of the basic clock signals as effective edges, the synchronous control module and the output control module take falling edges of the basic clock signals as effective edges, or The counting control module and the operation control module take the falling edge of the basic clock signal as an effective edge, and the synchronous control module and the output control module take the rising edge of the basic clock signal as an effective edge.
2. 2. The digital phase-locked loop circuit of claim 1, wherein the synchronization control module is further configured to: Generating a first characterization signal using a first D flip-flop based on the base clock signal and the input periodic signal; generating a second characterization signal using a second D flip-flop based on the base clock signal and the first characterization signal, and The input characterization signal is generated using a first and gate based on the inverse of the second characterization signal and the first characterization signal.
3. 3. The digital phase-locked loop circuit of claim 1, wherein the count control module is further configured to: Counting the number of cycles of the base clock signal with a clock counter when the input characterization signal is at a non-active level; And when the input characterization signal is at an effective level, updating the counting result of the clock counter to the clock counting result and resetting the clock counter.
4. 4. The digital phase-locked loop circuit of claim 1, wherein the operational control module is further configured to: initializing the basic clock control variable based on a preset frequency multiplication coefficient between the frequency of the output clock signal and the frequency of the input periodic signal when the input characterization signal is at an effective level, and And updating the basic clock control variable based on a preset frequency multiplication coefficient between the frequency of the output clock signal and the frequency of the input periodic signal when the input characterization signal is at a non-effective level.
5. 5. The digital phase-locked loop circuit of claim 4, wherein the operational control module is further configured to: Calculating an updated variable value of the basic clock control variable based on a variable value temporarily updated by the basic clock control variable on a previous valid edge of the basic clock signal and a preset frequency multiplication coefficient between the frequency of the output clock signal and the frequency of the input periodic signal, and The base clock control variable is updated with the calculated update variable value at the time the current active edge of the base clock signal comes.
6. 6. The digital phase-locked loop circuit of claim 1, wherein the operational control module is further configured to: initializing the output clock control variable based on the clock count result when the input characterization signal is at an active level, and The output clock control variable is updated based on the clock count result when the input characterization signal is at a non-active level.
7. 7. The digital phase-locked loop circuit of claim 6, wherein the operational control module is further configured to: Calculating an updated variable value of the output clock control variable based on the variable value of the output clock control variable that was updated at a previous valid edge of the base clock signal, the clock count result, and the output control signal, wherein the output control signal characterizes a magnitude-versus-relationship between the base clock control variable and the variable value of the output clock control variable that was updated at the previous valid edge of the base clock signal, and The output clock control variable is updated with the calculated update variable value at the time the current active edge of the base clock signal comes.
8. 8. The digital phase-locked loop circuit of claim 7, wherein the output control signal is a logic 1 when the base clock control variable is greater than the output clock control variable and is a logic 0 when the base clock control variable is not greater than the output clock control variable.
9. 9. The digital phase-locked loop circuit of claim 1, wherein the output control module is further configured to: Generating a variable comparison signal using a comparator based on the base clock control variable and the output clock control variable; Generating the output control signal using a third D flip-flop based on the base clock signal and the variable comparison signal, and The output clock signal is generated using a second and gate based on the base clock signal and the output control signal.
10. 10. A control method implemented by a digital phase-locked loop circuit, comprising: Generating an input characterization signal that characterizes a periodic variation of the input periodic signal relative to a base clock signal based on the base clock signal and the input periodic signal; Generating a clock count result characterizing a multiple relationship between a period of the input characterization signal and a period of the base clock signal based on the base clock signal and the input characterization signal; Generating a basic clock control variable based on a preset frequency multiplication coefficient between the frequency of the output clock signal and the frequency of the input periodic signal, and generating an output clock control variable based on the clock count result, and Generating an output control signal based on the base clock control variable and the output clock control variable, and generating an output clock signal based on the output control signal and the base clock signal, wherein The process of generating the clock count result and the process of generating the base clock control variable and the output clock control variable take a rising edge of the base clock signal as an active edge, the process of generating the input characterization signal and the process of generating the output clock signal take a falling edge of the base clock signal as an active edge, or The process of generating the clock count result and the process of generating the base clock control variable and the output clock control variable take a falling edge of the base clock signal as an active edge, and the process of generating the input characterization signal and the process of generating the output clock signal take a rising edge of the base clock signal as an active edge.
11. 11. The control method of claim 10, wherein generating the input characterizing signal comprises: Generating a first characterization signal using a first D flip-flop based on the base clock signal and the input periodic signal; generating a second characterization signal using a second D flip-flop based on the base clock signal and the first characterization signal, and The input characterization signal is generated using a first and gate based on the inverse of the second characterization signal and the first characterization signal.
12. 12. The control method of claim 10, wherein the process of generating the clock count result comprises: Counting the number of cycles of the base clock signal with a clock counter when the input characterization signal is at a non-active level; And when the input characterization signal is at an effective level, updating the counting result of the clock counter to the clock counting result and resetting the clock counter.
13. 13. The control method of claim 10, wherein generating the base clock control variable comprises: initializing the basic clock control variable based on a preset frequency multiplication coefficient between the frequency of the output clock signal and the frequency of the input periodic signal when the input characterization signal is at an effective level, and And updating the basic clock control variable based on a preset frequency multiplication coefficient between the frequency of the output clock signal and the frequency of the input periodic signal when the input characterization signal is at a non-effective level.
14. 14. The control method of claim 13, wherein updating the base clock control variable comprises: Calculating an updated variable value of the basic clock control variable based on a variable value temporarily updated by the basic clock control variable on a previous valid edge of the basic clock signal and a preset frequency multiplication coefficient between the frequency of the output clock signal and the frequency of the input periodic signal, and The base clock control variable is updated with the calculated update variable value at the time the current active edge of the base clock signal comes.
15. 15. The control method of claim 10, wherein generating the output clock control variable comprises: initializing the output clock control variable based on the clock count result when the input characterization signal is at an active level, and The output clock control variable is updated based on the clock count result when the input characterization signal is at a non-active level.
16. 16. The control method of claim 15, wherein updating the output clock control variable comprises: Calculating an updated variable value of the output clock control variable based on the variable value of the output clock control variable that was updated at a previous valid edge of the base clock signal, the clock count result, and the output control signal, wherein the output control signal characterizes a magnitude-versus-relationship between the base clock control variable and the variable value of the output clock control variable that was updated at the previous valid edge of the base clock signal, and The output clock control variable is updated with the calculated update variable value at the time the current active edge of the base clock signal comes.
17. 17. The control method of claim 16, wherein the output control signal is a logic 1 when the base clock control variable is greater than the output clock control variable and is a logic 0 when the base clock control variable is not greater than the output clock control variable.
18. 18. The control method of claim 10, wherein the process of generating the output clock signal comprises: Generating a variable comparison signal using a comparator based on the base clock control variable and the output clock control variable; Generating the output control signal using a third D flip-flop based on the base clock signal and the variable comparison signal, and The output clock signal is generated using a second and gate based on the base clock signal and the output control signal.

Description

Digital phase-locked loop circuit Technical Field The present invention relates to the field of circuits, and more particularly to a digital phase locked loop circuit. Background Phase locked loop circuits are a common type of circuit that may be used to generate an output clock signal based on an input periodic signal that is synchronized (both in frequency and phase) with the input periodic signal. Fig. 1 shows a schematic block diagram of a conventional analog phase-locked loop circuit. As shown in fig. 1, the analog phase-locked loop circuit includes three parts, namely a phase detector, a loop filter, and a voltage-controlled oscillator, wherein when the frequency of the input periodic signal Sin changes, the loop filter cannot rapidly adjust the voltage provided to the voltage-controlled oscillator according to the change of the frequency of the input periodic signal Sin, the frequency of the output clock signal Sout generated by the voltage-controlled oscillator oscillates to a larger extent and requires a longer adjustment time to achieve synchronization with the frequency of the input periodic signal Sin, and the analog phase-locked loop circuit is not suitable for the case that the frequency range of the input periodic signal is wider due to the limitation of the filtering parameter of the loop filter. Disclosure of Invention A digital phase-locked loop circuit according to an embodiment of the invention includes a synchronization control module configured to generate an input characterization signal that characterizes a periodic variation of an input periodic signal with respect to a base clock signal based on the base clock signal and the input periodic signal, a count control module configured to generate a clock count result that characterizes a multiple relationship between a period of the input characterization signal and a period of the base clock signal based on the base clock signal and the input characterization signal, an operation control module configured to generate a base clock control variable based on a preset frequency multiplication coefficient between a frequency of an output clock signal and a frequency of the input periodic signal and to generate an output clock control variable based on the clock count result, and an output control module configured to generate an output control signal based on the base clock control variable and the output clock control variable and to generate the output clock signal based on the output control signal and the base clock signal. The digital phase-locked loop circuit according to the embodiment of the invention can realize the synchronization (synchronization in two aspects of frequency and phase) between the output clock signal and the input periodic signal in a time far shorter than the adjustment time of the analog phase-locked loop circuit, and the loop oscillation problem of the analog phase-locked loop circuit does not exist. Drawings The invention will be better understood from the following description of specific embodiments thereof, taken in conjunction with the accompanying drawings, in which: Fig. 1 shows a schematic block diagram of a conventional analog phase-locked loop circuit. Fig. 2 shows a schematic block diagram of a digital phase locked loop circuit according to an embodiment of the invention. FIG. 3 illustrates a schematic diagram of an example implementation of the synchronization control module shown in FIG. 2; FIG. 4 illustrates waveforms of a plurality of signals associated with the synchronization control module shown in FIG. 3; FIG. 5 illustrates a schematic diagram of an example implementation of the count control module shown in FIG. 2; FIG. 6 illustrates a schematic diagram of a partial example implementation of the arithmetic control module shown in FIG. 2; FIG. 7 illustrates a schematic diagram of a partial example implementation of the arithmetic control module shown in FIG. 2; FIG. 8 illustrates a schematic diagram of an example implementation of the output control module shown in FIG. 2; fig. 9 shows a control flow diagram of a digital phase locked loop circuit according to an embodiment of the invention; fig. 10 shows waveforms of a plurality of signals related to the output control module shown in fig. 8. Detailed Description Features and exemplary embodiments of various aspects of the invention are described in detail below. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the invention by showing examples of the invention. The present invention is in no way limited to any particular configuration and algorithm set forth below, but rather covers any modification, substitution