CN-114356681-B - Fault processing method and device in chip verification process and electronic equipment

CN114356681BCN 114356681 BCN114356681 BCN 114356681BCN-114356681-B

Abstract

The application provides a fault processing method, a device and electronic equipment in a chip verification process, which comprise the steps of carrying out fault identification in the chip verification process, and acquiring fault information of a fault in response to the identification of the fault; determining a target fault debugging strategy matched with the fault information, executing the target fault debugging strategy to debug the fault, and continuing the chip verification process from the position point of the fault in response to the completion of the fault debugging. According to the application, fault debugging in the chip verification process is realized, modification of the source code corresponding to the chip verification and re-simulation of the modified source code are avoided, the fault repairing time in the chip verification process is effectively shortened, and the chip verification efficiency is further improved.

Inventors

SUO JIAN
WANG ZHENG

Assignees

北京爱芯科技有限公司
北京爱芯科技有限公司

Dates

Publication Date: 20260421
Application Date: 20211207
Priority Date: 20211207

Claims (10)

1. A method for processing faults in a chip verification process, comprising the steps of: performing fault identification in the chip verification process, and acquiring fault information of a fault in response to the identification of the fault; Determining a target fault debugging strategy matched with the fault information; executing the target fault debugging strategy, and carrying out fault debugging on the fault; Responding to the fault debugging ending, and continuing the chip verification process from the fault position point; Wherein the determining a target fault commissioning policy that matches the fault information includes: determining a fault object and a corresponding fault type in the chip verification process from the fault information; determining the target fault debugging strategy according to the fault object and the fault type; wherein said determining said target fault debug policy according to said fault object and said fault type comprises: Responding to the fault type as the configuration fault of the fault object in the chip verification process, modifying the configuration parameters of the fault object, and taking the configuration parameters as the target fault debugging strategy; Responding to the fault type as the operation fault of the fault object in the chip verification process, calling a matched debugging test sequence, debugging the operation fault of the fault object according to the operation result of the debugging test sequence, and taking the operation fault as the target fault debugging strategy; And calling a corresponding function test sequence in response to the failure type being the failure of the failure object in the chip verification process, supplementing the failure function to be verified of the failure object according to the operation result of the function test sequence, and taking the failure type as the target failure debugging strategy.
2. The method of claim 1, wherein said executing said target fault-debug policy, fault-debugging said fault, comprises: In response to identifying the fault, starting a general debugging library, wherein the general debugging library is connected with a chip verification platform; receiving a target fault debugging instruction corresponding to the target fault debugging strategy transmitted by the general debugging library, and executing the target fault debugging strategy according to the target fault debugging instruction.
3. The method of claim 2, wherein the launching the universal debug library comprises: Triggering the running of a starting code to start the universal debugging library, wherein the starting code is compiled in the code of the chip verification platform, or Executing the script and starting the universal debugging library.
4. A method according to claim 2 or 3, wherein said executing said target fault-debug policy, after fault-debugging said fault, further comprises: receiving a debugging detection instruction transmitted by the general debugging library; and operating the debugging detection instruction, and determining that the fault debugging in the chip verification process is completed according to the operation result of the debugging detection instruction.
5. A fault handling device in a chip verification process, comprising: The identification module is used for carrying out fault identification in the chip verification process, and acquiring fault information of the fault in response to the identification of the fault; the determining module is used for determining a target fault debugging strategy matched with the fault information; the debugging module is used for executing the target fault debugging strategy and carrying out fault debugging on the fault; the verification module is used for responding to the fault debugging completion and continuing the chip verification process from the fault position point; Wherein, the determining module is further configured to: determining a fault object and a corresponding fault type in the chip verification process from the fault information; determining the target fault debugging strategy according to the fault object and the fault type; The determining module is further configured to: Responding to the fault type as the configuration fault of the fault object in the chip verification process, modifying the configuration parameters of the fault object, and taking the configuration parameters as the target fault debugging strategy; Responding to the fault type as the operation fault of the fault object in the chip verification process, calling a matched debugging test sequence, debugging the operation fault of the fault object according to the operation result of the debugging test sequence, and taking the operation fault as the target fault debugging strategy; And calling a corresponding function test sequence in response to the failure type being the failure of the failure object in the chip verification process, supplementing the failure function to be verified of the failure object according to the operation result of the function test sequence, and taking the failure type as the target failure debugging strategy.
6. The apparatus of claim 5, wherein the debug module is further to: In response to identifying the fault, starting a general debugging library, wherein the general debugging library is connected with a chip verification platform; receiving a target fault debugging instruction corresponding to the target fault debugging strategy transmitted by the general debugging library, and executing the target fault debugging strategy according to the target fault debugging instruction.
7. The apparatus of claim 6, wherein the debug module is further to: Triggering the running of a starting code to start the universal debugging library, wherein the starting code is compiled in the code of the chip verification platform, or Executing the script and starting the universal debugging library.
8. The apparatus of claim 6 or 7, wherein the debug module is further to: receiving a debugging detection instruction transmitted by the general debugging library; and operating the debugging detection instruction, and determining that the fault debugging in the chip verification process is completed according to the operation result of the debugging detection instruction.
9. An electronic device, comprising: At least one processor, and A memory communicatively coupled to the at least one processor, wherein, The memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-4.
10. A readable storage medium storing computer instructions for causing the computer to perform the method of any one of claims 1-4.

Description

Fault processing method and device in chip verification process and electronic equipment Technical Field The present application relates to the field of chip verification, and in particular, to a fault processing method and apparatus in a chip verification process, and an electronic device. Background With the development of society, chip verification is increasingly important. Along with the increase of the complexity of chip design, the verification time of each module of the chip is increased, so that the repair time of faults in the chip verification process is increased, and the chip verification efficiency is affected. Therefore, how to improve the efficiency of chip verification is a problem to be solved at present. Disclosure of Invention The object of the present application is to solve at least to some extent one of the technical problems in the art described above. The first aspect of the application provides a fault processing method in a chip verification process, which comprises the steps of carrying out fault identification in the chip verification process, obtaining fault information of a fault in response to the identification of the fault, determining a target fault debugging strategy matched with the fault information, executing the target fault debugging strategy to carry out fault debugging on the fault, and continuing the chip verification process from a fault position point in response to the completion of fault debugging. The fault processing method in the chip verification process provided by the first aspect of the application also has the following technical characteristics that: according to the embodiment of the application, the method for determining the target fault debugging strategy matched with the fault information comprises the steps of determining a fault object and a corresponding fault type in the chip verification process from the fault information, and determining the target fault debugging strategy according to the fault object and the fault type. According to the method, the device and the system, the target fault debugging strategy is determined according to the fault object and the fault type, the method comprises the steps of responding to the fault type which is a configuration fault of the fault object in the chip verification process, modifying configuration parameters of the fault object and serving as the target fault debugging strategy, responding to the fault type which is an operation fault of the fault object in the chip verification process, calling a matched debugging test sequence, debugging the operation fault of the fault object according to an operation result of the debugging test sequence and serving as the target fault debugging strategy, responding to the fault type which is a verification missing fault of the fault object in the chip verification process, calling a corresponding function test sequence, supplementing a missing function to be verified of the fault object according to an operation result of the function test sequence and serving as the target fault debugging strategy. According to the embodiment of the application, the executing the target fault debugging strategy for fault debugging of the fault comprises the steps of starting a general debugging library in response to the fault identification, wherein the general debugging library is connected with the chip verification platform, receiving a target fault debugging instruction corresponding to the target fault debugging strategy transmitted by the general debugging library, and executing the target fault debugging strategy according to the target fault debugging instruction. According to the embodiment of the application, the method for starting the universal debugging library comprises the steps of triggering a starting code to run and starting the universal debugging library, wherein the starting code is compiled in a code of a chip verification platform, or executing a script and starting the universal debugging library. According to an embodiment of the application, after the target debugging processing strategy is executed and the fault is debugged, the method further comprises the steps of receiving a debugging detection instruction transmitted by the universal debugging library, operating the debugging detection instruction, and determining that the fault debugging in the chip verification process is completed according to an operation result of the debugging detection instruction. The application provides a fault processing device in a chip verification process, which comprises an identification module, a determination module, a debugging module and a verification module, wherein the identification module is used for carrying out fault identification in the chip verification process, acquiring fault information of a fault in response to the identification of the fault, the determination module is used for determining a target fault debugging strategy matched with the fa