CN-114373750-B - Semiconductor structure and forming method thereof

Abstract

A semiconductor structure and a forming method thereof are provided, the forming method comprises the steps of providing a substrate, a grid structure, a grid cap layer, side walls, a source-drain doping area, a bottom dielectric layer, a source-drain contact layer and a source-drain cap layer, forming a top dielectric layer on the bottom dielectric layer to cover the grid cap layer, the source-drain cap layer and the side walls, forming a source-drain through hole penetrating through the top dielectric layer and the source-drain cap layer of a first area to expose the top surface of the source-drain contact layer, forming a grid through hole penetrating through the top dielectric layer and the grid cap layer of a second area to expose the top surface of the grid structure, removing part of the side walls of the corresponding areas in the step of forming any one or two of the source-drain through hole and the grid through hole, forming an etching blocking layer which is located on the side walls of the corresponding through holes and covers the tops of the side walls, and forming a grid plug located in the grid through hole and a source-drain plug located in the source-drain through hole. The embodiment of the invention is beneficial to improving the performance of the semiconductor structure.

Inventors

• JIN JISONG

Assignees

• 中芯国际集成电路制造(上海)有限公司
• 中芯国际集成电路制造(北京)有限公司

Dates

Publication Date

20260505

Application Date

20201014

Claims (20)

1. 1. A semiconductor structure, comprising: The substrate comprises a first region for forming a source and drain plug and a second region for forming a gate plug; a gate structure discrete on the substrate; the grid cap layer is positioned on the top of the grid structure; The side wall is positioned on the side walls of the grid structure and the grid cap layer; the source-drain doped regions are positioned in the substrate at two sides of the grid structure; The bottom dielectric layer is positioned at the side part of the grid structure and covers the source-drain doped region; the source-drain contact layer is positioned in the bottom dielectric layer and is contacted with the source-drain doped region; The source-drain cap layer is positioned on the top of the source-drain contact layer; the top dielectric layer is positioned on the bottom dielectric layer and covers the grid electrode cap layer, the source drain cap layer and the side wall; The source-drain plug penetrates through the top dielectric layer and the source-drain cap layer which are positioned in the first region, and the source-drain plug is contacted with the top of the source-drain contact layer; the gate plug penetrates through the top dielectric layer and the gate cap layer which are positioned in the second area, and is contacted with the top of the gate structure; The etching barrier layer is positioned on the side wall of any one or two of the source drain plug and the grid plug and covers the top surface of the side wall of the corresponding area, and the etching barrier layer is formed by removing part of the height side wall of the corresponding area in the step of forming any one or two of the source drain through hole and the grid through hole; And the interconnection line is positioned in the top dielectric layer on the source-drain plug and the gate plug, and is contacted with the tops of the source-drain plug and the gate plug.
2. 2. The semiconductor structure of claim 1, wherein the interconnect line is integral with the source drain plug and the gate plug.
3. 3. The semiconductor structure of claim 1, wherein the etch stop layer comprises a first etch stop layer between sidewalls of the source drain plug and sidewalls of an adjacent gate cap layer, the first etch stop layer covering a top surface of a sidewall of the first region.
4. 4. The semiconductor structure of claim 1, wherein the etch stop layer comprises a second etch stop layer between the gate plug sidewalls and sidewalls of adjacent source drain cap layers, the etch stop layer covering top surfaces of sidewalls of the second region.
5. 5. The semiconductor structure of claim 1, wherein a bottom surface of the etch stop layer is lower than bottom surfaces of the source drain cap layer and the gate cap layer.
6. 6. The semiconductor structure of claim 1, wherein the etch stop layer protrudes from a sidewall of the sidewall along a direction perpendicular to an extension of the gate structure on a projection plane parallel to the substrate.
7. 7. The semiconductor structure of claim 1, wherein a material of the etch stop layer has an etch selectivity to a material of any one or more of the gate cap layer, the sidewall, and the source drain cap layer.
8. 8. The semiconductor structure of claim 1, wherein the material of the etch stop layer comprises one or more of silicon nitride, silicon carbonitride, silicon oxycarbide, silicon carbide, aluminum nitride, and aluminum oxide.
9. 9. A method of forming a semiconductor structure, comprising: A substrate is provided, which comprises a first area for forming a source-drain plug and a second area for forming a gate plug, wherein a discrete gate structure is formed on the substrate, a gate cap layer is formed on the top of the gate structure, side walls are formed on the gate structure and the side walls of the gate cap layer, source-drain doping areas are formed in the substrate on two sides of the gate structure, a bottom dielectric layer for covering the source-drain doping areas is formed on the side parts of the gate structure, a source-drain contact layer contacted with the source-drain doping areas is formed in the bottom dielectric layer, and a source-drain cap layer is formed on the top of the source-drain contact layer; Forming a top dielectric layer on the bottom dielectric layer to cover the grid electrode cap layer, the source drain cap layer and the side wall; forming a source-drain through hole penetrating through the top dielectric layer and the source-drain cap layer of the first region, and exposing the top surface of the source-drain contact layer; Forming a gate through hole penetrating through the top dielectric layer and the gate cap layer of the second region, and exposing the top surface of the gate structure; removing part of the height side wall of the corresponding region in the step of forming any one or two of the source drain through hole and the grid through hole, and forming an etching barrier layer which is positioned on the side wall of the corresponding through hole and covers the top of the side wall; Forming a gate plug in the gate through hole and a source and drain plug in the source and drain through hole.
10. 10. The method of forming a semiconductor structure of claim 9, further comprising forming an interconnect trench through a portion of a thickness of said top dielectric layer after forming said top dielectric layer and prior to forming said source drain and gate vias, said interconnect trench being located above said first and second regions; Forming the source-drain through holes penetrating through the top dielectric layer and the source-drain cap layer at the bottom of the interconnection groove, wherein the source-drain through holes are communicated with the interconnection groove; forming the gate through hole penetrating through the top dielectric layer and the gate cap layer at the bottom of the interconnection groove, wherein the gate through hole is communicated with the interconnection groove; The method for forming the semiconductor structure further comprises the step of forming an interconnection line in the interconnection groove in the step of forming the gate plug and the source-drain plug, wherein the interconnection line is in contact with the tops of the gate plug and the source-drain plug.
11. 11. The method of forming a semiconductor structure according to claim 9, wherein in the step of forming the source-drain via hole, a portion of the height sidewall of the first region is removed, and a first etching barrier layer is formed on the sidewall of the source-drain via hole and covers the top of the sidewall; the step of forming the source drain through hole and the first etching blocking layer comprises the steps of forming an initial source drain through hole penetrating through a top dielectric layer of the first area, removing part of a height side wall exposed by the initial source drain through hole to enable the source drain cover cap layer, an adjacent grid cover cap layer and the top of the residual side wall to form a first gap, forming the first etching blocking layer in the first gap, and removing the source drain cover cap layer below the initial source drain through hole after the first etching blocking layer is formed to form the source drain through hole.
12. 12. The method of forming a semiconductor structure according to claim 9, wherein in the step of forming the source-drain via hole, a portion of the height sidewall of the first region is removed, and a first etching barrier layer is formed on the sidewall of the source-drain via hole and covers the top of the sidewall; The step of forming the source drain through hole and the first etching blocking layer comprises the steps of forming an initial source drain through hole penetrating through a top dielectric layer of the first area, removing a source drain cap layer below the initial source drain through hole, removing a part of a height side wall exposed by the initial source drain through hole, and forming the first etching blocking layer on the side wall of the grid cap layer exposed by the initial source drain through hole to enable the initial source drain through hole to form the source drain through hole.
13. 13. The method of forming a semiconductor structure of claim 9, wherein in the step of forming the gate via, removing a portion of the height sidewall of the second region to form a second etch stop layer on the sidewall of the gate via and covering the top of the sidewall; The step of forming the gate through hole and the second etching barrier layer comprises the steps of forming an initial gate through hole penetrating through a top dielectric layer located in the second area, removing part of the height side wall exposed by the initial gate through hole to enable the gate cap layer, the adjacent source drain cap layer and the tops of the rest side walls to form a second gap, forming the second etching barrier layer in the second gap, and removing the gate cap layer below the initial gate through hole after forming the second etching barrier layer to form the gate through hole.
14. 14. The method of forming a semiconductor structure of claim 9, wherein in the step of forming the gate via, removing a portion of the height sidewall of the second region to form a second etch stop layer on the sidewall of the gate via and covering the top of the sidewall; The step of forming the gate through hole and the second etching barrier layer comprises the steps of forming an initial gate through hole penetrating through a top dielectric layer of the second area, removing a gate cap layer below the initial gate through hole, removing a part of a height side wall exposed by the initial gate through hole, and forming the second etching barrier layer on the side wall of a source drain cap layer exposed by the initial gate through hole to enable the initial gate through hole to form the gate through hole.
15. 15. The method of forming a semiconductor structure of claim 11, wherein forming the first etch stop layer comprises filling a first etch stop film in the first gap using a deposition process, the first etch stop film also being located on the bottom and sidewalls of the initial source drain via; And removing the first etching barrier film positioned on the bottom and the side wall of the initial source drain through hole by adopting an etching process, and using the remaining first etching barrier film positioned in the first gap as the first etching barrier layer.
16. 16. The method of forming a semiconductor structure of claim 13, wherein forming the second etch stop layer comprises filling a second etch stop film in the second gap using a deposition process, the second etch stop film also being located on the bottom and sidewalls of the initial gate via; And removing the second etching barrier film positioned on the bottom and the side wall of the initial gate through hole by adopting an etching process, and using the second etching barrier film positioned in the second gap as the second etching barrier layer.
17. 17. The method of forming a semiconductor structure of claim 15 or 16, wherein the deposition process comprises an atomic layer deposition process.
18. 18. The method of forming a semiconductor structure as claimed in claim 15 or 16, wherein the etching process is an isotropic etching process.
19. 19. The method of claim 9, wherein in the step of removing a portion of the height sidewall of the corresponding region, a portion of the thickness gate cap layer and a portion of the thickness source drain cap layer on the sidewall of the sidewall are further etched along a direction parallel to the substrate surface and perpendicular to the extending direction of the gate structure.
20. 20. The method of forming a semiconductor structure of claim 9, wherein removing a portion of the height sidewall of the corresponding region comprises one or both of dry etching and wet etching.

Description

Semiconductor structure and forming method thereof Technical Field Embodiments of the present disclosure relate to semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same. Background With the continued development of integrated circuit fabrication technology, the demands on the degree of integration and performance of integrated circuits are becoming ever higher. In order to improve the integration level and reduce the cost, the critical dimensions of the components are continuously reduced, and the circuit density inside the integrated circuit is increasingly high, so that the wafer surface cannot provide enough area to manufacture the required interconnection line. In order to meet the requirements of the interconnect lines with reduced critical dimensions, the different metal layers or the conduction between the metal layers and the substrate is realized through the interconnect structure. The interconnect structure includes an interconnect line and a contact hole plug formed within the contact opening. The contact hole plugs are connected with the semiconductor device, and the interconnection lines realize the connection between the contact hole plugs, so that a circuit is formed. The contact hole plug in the transistor structure comprises a gate contact hole plug positioned on the surface of the gate structure and used for realizing the connection between the gate structure and an external circuit, and also comprises a source-drain contact hole plug positioned on the surface of the source-drain doped region and used for realizing the connection between the source-drain doped region and the external circuit. Currently, to achieve further reduction of transistor area, an active gate Contact plug (Contact Over ACTIVE GATE, COAG) process is introduced. Compared with the traditional gate contact plug positioned above the gate structure of the isolation region, the COAG process can enable the gate contact plug to be positioned above the gate structure of the active region (ACTIVE AREA, AA), so that the area of the chip is further saved. However, the device formed by the COAG process still has the problem of poor performance. Disclosure of Invention The embodiment of the invention solves the problem of providing a semiconductor structure and a forming method thereof, which improves the performance of the semiconductor structure. In order to solve the problems, the embodiment of the invention provides a semiconductor structure, which comprises a substrate, a grid structure, a grid cap layer, side walls, a source-drain doped region, a bottom dielectric layer, a source-drain contact layer, a top dielectric layer, a bottom dielectric layer, a source-drain cap layer, a side wall, an etching cap layer and a drain plug, wherein the substrate comprises a first region for forming a source-drain plug and a second region for forming a grid plug, the grid structure is separated on the substrate, the grid cap layer is positioned at the top of the grid structure, the side walls of the grid structure and the grid cap layer, the source-drain doped region is positioned in the substrate on two sides of the grid structure, the bottom dielectric layer is positioned at the side of the grid structure and covers the source-drain doped region, the source-drain contact layer is positioned in the bottom dielectric layer and is in contact with the source-drain doped region, the source-cap layer is positioned at the top of the source-drain contact layer, the top dielectric layer is positioned on the bottom dielectric layer and the bottom dielectric layer is positioned on the bottom dielectric layer and covers the grid cap layer and the side walls of the grid cap layer, the source-drain plug is in contact with the top of the grid cap layer, and the top of the grid cap layer is positioned at the top of the grid cap layer and the grid cap layer is positioned at the top of the grid cap layer. Correspondingly, the embodiment of the invention also provides a method for forming the semiconductor structure, which comprises the steps of providing a substrate, forming a first region for forming a source-drain plug and a second region for forming a gate plug, forming a discrete gate structure on the substrate, forming a gate cap layer on the top of the gate structure, forming side walls on the side walls of the gate structure and the gate cap layer, forming source-drain doped regions in the substrate on two sides of the gate structure, forming a bottom dielectric layer covering the source-drain doped regions on the side of the gate structure, forming a source-drain contact layer in the bottom dielectric layer, forming a source-drain cap layer on the top of the source-drain contact layer, forming a top dielectric layer on the bottom dielectric layer, covering the gate cap layer, the source-drain cap layer and the side walls, forming a top dielectric layer penetrating the first region and th