CN-114388558-B - Display substrate and display device

CN114388558BCN 114388558 BCN114388558 BCN 114388558BCN-114388558-B

Abstract

A display substrate and a display device include a substrate, a display region disposed on the substrate and including a plurality of pixel driving units, each of the plurality of pixel driving units including a threshold compensation transistor, a first light emitting control transistor, an active layer of the threshold compensation transistor including a first channel region corresponding to a first gate electrode, a second channel region corresponding to a second gate electrode, and an intermediate region between the first channel region and the second channel region, a plurality of light shielding patterns having first ends for receiving voltage signals, and a second end of at least one of the plurality of light shielding patterns at least partially overlapping an intermediate region of the threshold compensation transistor of an outermost 1 st pixel driving unit of at least one row of pixel driving units in a direction perpendicular to the substrate. The display substrate can introduce a small pepper design structure into the first column of pixel driving units at the outermost side of the display area, so that the leakage capacity of the double-gate transistor is reduced.

Inventors

SUN KAIPENG
WANG BINYAN
CAI JIANCHANG
WU CHAO
LONG YUE
HUANG YAO

Assignees

京东方科技集团股份有限公司
成都京东方光电科技有限公司

Dates

Publication Date: 20260505
Application Date: 20201019

Claims (20)

1. A display substrate, comprising: A substrate base; A display region disposed on the substrate, and including a plurality of pixel driving units arranged in a plurality of rows and a plurality of columns, wherein each of the plurality of pixel driving units includes a threshold compensation transistor, a first light emitting control transistor, and a storage capacitor, the threshold compensation transistor is respectively connected to the first light emitting control transistor and the storage capacitor, the threshold compensation transistor includes a first gate and a second gate, an active layer of the threshold compensation transistor includes a first channel region corresponding to the first gate, a second channel region corresponding to the second gate, and an intermediate region between the first channel region and the second channel region, the first channel region and the second channel region being connected through the intermediate region; A plurality of light shielding patterns, wherein each light shielding pattern includes a first end and a second end, the first ends of the plurality of light shielding patterns are used for receiving voltage signals, and the second end of at least one light shielding pattern in the plurality of light shielding patterns is at least partially overlapped with a middle area of a threshold value compensation transistor of an outermost 1 st pixel driving unit of at least one row of pixel driving units in a direction perpendicular to the substrate base plate; The display substrate further comprises a peripheral area at least partially surrounding the display area, a plurality of first power lines positioned in the display area and first power line edge wires positioned in the peripheral area, wherein the plurality of first power lines extend along a first direction and are configured to be connected with each column of pixel driving units in the plurality of pixel driving units so as to respectively provide first power supply voltages for the column of pixel driving units, the first power line edge wires are configured to be connected with the plurality of first power lines so as to provide the first power supply voltages for the first power lines, the first power line edge wires comprise first subconductors extending along the first direction, the first subconductors are arranged on one side close to the 1 st pixel driving unit of the plurality of pixel driving units, and the width of the first subconductors is larger than that of the first power lines; The voltage signal includes the first supply voltage; The plurality of light shielding patterns comprise a plurality of first light shielding patterns and a plurality of fourth light shielding patterns, and the length of the first light shielding patterns is larger than that of the fourth light shielding patterns; A first end of the plurality of first light shielding patterns is connected with the first sub-wires, and a second end of at least one first light shielding pattern of the plurality of first light shielding patterns is at least partially overlapped with a middle area of a threshold compensation transistor of a 1 st pixel driving unit of the at least one row of pixel driving units in a direction perpendicular to the substrate base plate; The second ends of the fourth light shielding patterns extend to adjacent pixel driving units positioned on one side of the corresponding pixel driving units, which is far away from the first sub-wires, and are at least partially overlapped with the middle area of the threshold value compensation transistor of the adjacent pixel driving units in the direction perpendicular to the substrate base plate; the display substrate further comprises a plurality of signal lines electrically connected with the pixel driving units respectively, wherein the pixel driving units are not arranged between the first light shielding pattern and the first sub-wires, and the first light shielding pattern and the signal lines are not overlapped in the direction perpendicular to the substrate.
2. The display substrate of claim 1, wherein the first power line edge trace includes a second sub-line extending in the first direction and disposed opposite the first sub-line, and third and fourth sub-lines extending in a second direction and disposed opposite.
3. The display substrate according to claim 2, further comprising a first electrode pattern electrically connected to at least one of the plurality of signal lines at the peripheral region and a second electrode pattern at the peripheral region; The first electrode pattern and the second electrode pattern are positioned at one side of the peripheral region, which is close to the 1 st pixel driving unit at the outermost side of the at least one row of pixel driving units; The first electrode pattern and the second electrode pattern are at least partially overlapped and insulated in a direction perpendicular to the plate surface of the substrate.
4. The display substrate according to claim 3, wherein the first electrode pattern is connected to the signal line through a via hole to compensate for a load capacitance of the signal line; the second electrode pattern is connected with the first power line through a via hole to receive the first power voltage.
5. The display substrate of claim 4, wherein the light shielding pattern further comprises at least one second light shielding pattern; wherein the first end of the at least one second light shielding pattern is connected with the second electrode pattern and integrally formed, A second end of the at least one second light shielding pattern at least partially overlaps an intermediate region of at least one threshold compensation transistor of a1 st pixel driving unit of at least one row of pixel driving units adjacent to the second electrode pattern in the second direction in a direction perpendicular to the substrate base plate.
6. The display substrate according to claim 5, wherein the number of pixels of at least one row of pixel driving units adjacent to the first electrode pattern or the second electrode pattern in the second direction is smaller than the number of pixels of one row of pixel driving units adjacent to the first electrode pattern or the second electrode pattern in the first direction.
7. The display substrate of claim 1, wherein an extension direction of the first light shielding pattern is different from an extension direction of the first sub-wires.
8. The display substrate of claim 5, wherein the plurality of signal lines comprise data lines or gate lines.
9. The display substrate of claim 8, wherein an orthographic projection of the data line on the substrate at least partially overlaps an orthographic projection of the storage capacitor on the substrate.
10. The display substrate of claim 9, further comprising a power connection trace on a side of the peripheral region adjacent to an outermost 1 st pixel drive unit of the at least one row of pixel drive units; the power connection wiring is connected with the first power line through a via hole so as to receive the first power voltage; The light shielding pattern further comprises at least one third light shielding pattern, wherein the first end of the at least one third light shielding pattern is connected with the power supply connection wiring, and the second end of the at least one third light shielding pattern at least partially overlaps with the middle area of the threshold compensation transistor of the 1 st pixel driving unit of at least one row of pixel driving units adjacent to the power supply connection wiring in the second direction in the direction vertical to the substrate base plate; the third light shielding pattern and the power connection trace do not overlap in a direction perpendicular to the substrate.
11. The display substrate according to claim 10, wherein the number of pixels of each row of pixel driving units adjacent to the power connection wiring in the second direction is smaller than the number of pixels of each row of pixel driving units adjacent to the power connection wiring in the first direction.
12. The display substrate of claim 10, further comprising a first switching electrode, wherein a first end of the first switching electrode is connected to the power connection trace through a via, and a second end of the first switching electrode is connected to the at least one third light shielding pattern through a via.
13. The display substrate of claim 1, wherein first ends of at least one light shielding pattern among the plurality of light shielding patterns are respectively connected with first power lines corresponding to an outermost 1 st pixel driving unit of the at least one row of pixel driving units to receive the first power voltage as the voltage signal.
14. The display substrate according to claim 1, further comprising an initialization signal line configured to supply an initialization signal to the plurality of pixel driving units; wherein the voltage signal includes the initialization signal.
15. The display substrate of claim 14, wherein each of the plurality of pixel driving units further comprises a first reset transistor and a second reset transistor; Wherein a first pole of the first reset transistor is connected with the initialization signal line to receive the initialization signal, a second pole of the first reset transistor is connected with the threshold compensation transistor, and a gate of the first reset transistor is connected with the first reset signal line to receive a first reset signal; The first pole of the second reset transistor is connected with the initialization signal line to receive the initialization signal, the second pole of the second reset transistor is connected with the first light emitting control transistor, and the grid electrode of the second reset transistor is connected with the second reset signal line to receive the second reset signal.
16. The display substrate of claim 15, further comprising a plurality of second transfer electrodes, a first insulating layer, a second insulating layer, and a third insulating layer, The first ends of the second switching electrodes are respectively connected with the initialization signal lines to receive the initialization signals, and the second ends of the second switching electrodes are respectively connected with the first poles of the first reset transistors of the 1 st pixel driving units at the outermost side of each row of pixel driving units through the first insulating layer, the second insulating layer and the third insulating layer; the first electrode of the first reset transistor of the outermost 1 st pixel driving unit is connected to the first ends of the plurality of light shielding patterns through vias penetrating the first insulating layer and the second insulating layer, respectively.
17. The display substrate of claim 15, wherein the pixel driving unit further comprises a driving transistor; The active layer of the first reset transistor and the active layer of the driving transistor at least partially overlap the first power line.
18. The display substrate of claim 8, wherein an area of the second light shielding pattern overlapping the first power line is larger than an area of the second light shielding pattern overlapping the data line in a direction perpendicular to the substrate.
19. The display substrate according to claim 12, wherein a signal line overlapping the first switching electrode does not overlap the power supply connection wiring in a direction perpendicular to the substrate, and a signal line overlapping the power supply connection wiring does not overlap the first switching electrode.
20. The display substrate according to claim 2, further comprising a connection portion extending in the second direction, the connection portion including a first portion connected between the first sub-conductor and the storage capacitor and a second portion connected between storage capacitors of adjacent two of a row of pixel driving units.

Description

Display substrate and display device Technical Field At least one embodiment of the present disclosure relates to a display substrate and a display device. Background The Organic Light-Emitting Diode (OLED) display device has the advantages of thin thickness, light weight, wide viewing angle, active Light emission, continuous and adjustable Light emission color, low cost, fast response speed, low energy consumption, low driving voltage, wide operating temperature range, simple production process, high Light emission efficiency, flexible display and the like, and is therefore increasingly widely applied to the display fields of mobile phones, tablet computers, digital cameras and the like. Disclosure of Invention The display substrate comprises a substrate, a display area and a plurality of light shielding patterns, wherein the display area is arranged on the substrate and comprises a plurality of pixel driving units which are arranged in a plurality of rows and a plurality of columns, each pixel driving unit comprises a threshold value compensation transistor, a first light emitting control transistor and a storage capacitor, the threshold value compensation transistor is respectively connected with the first light emitting control transistor and the storage capacitor, the threshold value compensation transistor comprises a first grid electrode and a second grid electrode, an active layer of the threshold value compensation transistor comprises a first channel region corresponding to the first grid electrode, a second channel region corresponding to the second grid electrode and an intermediate area which is positioned between the first channel region and the second channel region, the first channel region and the second channel region are connected through the intermediate area, each light shielding pattern comprises a first end and a second end, the first end of each light shielding pattern is used for receiving a voltage signal, and at least one light shielding pattern of the plurality of light shielding patterns overlaps with at least one pixel driving unit of the first pixel driving unit in the middle area in the direction perpendicular to at least one row of the substrate. For example, the display substrate provided in at least one embodiment of the present disclosure further includes a peripheral region at least partially surrounding the display region, a plurality of first power lines located in the display region and a first power line edge trace located in the peripheral region, the plurality of first power lines extending along a first direction and configured to be connected to each column of pixel driving units of the plurality of pixel driving units to respectively provide the first power voltage to each column of pixel driving units, the first power line edge trace configured to be connected to the plurality of first power lines to provide the first power voltage to the first power lines, and the voltage signal includes the first power voltage. For example, in a display substrate provided in at least one embodiment of the present disclosure, the plurality of light shielding patterns includes a plurality of first light shielding patterns, the first power line edge trace includes first and second sub-wires extending in the first direction and disposed opposite to each other, and third and fourth sub-wires extending in the second direction and disposed opposite to each other, the first sub-wire is disposed at a side near a 1 st pixel driving unit of the plurality of pixel driving units, a first end of the plurality of first light shielding patterns is connected to the first sub-wire to receive the first power voltage, and a second end of at least one first light shielding pattern of the plurality of first light shielding patterns is at least partially overlapped with an intermediate region of a threshold compensation transistor of the 1 st pixel driving unit of the at least one row of pixel driving units in a direction perpendicular to the substrate. For example, the display substrate provided in at least one embodiment of the present disclosure further includes a plurality of signal lines electrically connected to the plurality of pixel driving units, respectively, a first electrode pattern electrically connected to at least one of the plurality of signal lines and located in the peripheral region, and a second electrode pattern located in the peripheral region, the first electrode pattern and the second electrode pattern being located at one side of the peripheral region near the outermost 1 st pixel driving unit of the at least one row of pixel driving units, the first electrode pattern and the second electrode pattern being at least partially overlapped and insulated in a direction perpendicular to a plate surface of the substrate. For example, in the display substrate provided in at least one embodiment of the present disclosure, the first electrode pattern is connected to the signal line t