CN-114446885-B - Preparation method of semiconductor device and semiconductor device

CN114446885BCN 114446885 BCN114446885 BCN 114446885BCN-114446885-B

Abstract

The invention provides a preparation method of a semiconductor device and the semiconductor device, wherein the method comprises the steps that a contact structure is formed on a semiconductor substrate and is electrically connected with a capacitor; forming an etching stop layer above a contact structure, forming a lamination of a sacrificial layer and a supporting layer above the etching stop layer, wherein the sacrificial layer and the supporting layer comprise at least one layer, performing ion implantation on the supporting layer after each forming of the supporting layer, performing annealing treatment on the supporting layer after ion implantation, forming a hard mask layer above the topmost supporting layer, implanting ions into the supporting layer, releasing stress between Si-O bonds by utilizing ion collision, removing residual film pressure of the supporting layer, performing annealing treatment on the supporting layer, forming a film with high compactness, avoiding bending, cracking or lifting phenomena of a capacitor electrode of a semiconductor device, and ensuring stability of a preparation process and overall performance of the semiconductor device without adjusting deposition conditions of the supporting layer.

Inventors

Jin Xuanyong
Guo Tiaoyuan
XU KANGYUAN
GAO JIANFENG
FAN ZHENGPING
YANG TAO
WANG WENWU
LI JUNFENG

Assignees

中国科学院微电子研究所
真芯(北京)半导体有限责任公司

Dates

Publication Date: 20260505
Application Date: 20201104

Claims (12)

1. A method of manufacturing a semiconductor device, the method comprising: providing a semiconductor substrate, wherein a contact structure is formed on the semiconductor substrate, and the contact structure is electrically connected with a capacitor; Forming an etch stop layer over the contact structure; Forming a stack of a sacrificial layer and a supporting layer above the etching stop layer, wherein the sacrificial layer and the supporting layer both comprise at least one layer, and the position relationship of the sacrificial layer and the supporting layer is cross stack; the method comprises the steps of forming a supporting layer, carrying out ion implantation on the supporting layer after forming the supporting layer each time, and carrying out annealing treatment on the supporting layer after ion implantation; forming a hard mask layer above the topmost support layer; The ion implantation of the support layer after each formation of the support layer comprises: At least one of Ar, H, he, N, O, C, si and B ions is implanted into the support layer formed at a time.
2. The method of claim 1, wherein sequentially forming a stack of a sacrificial layer and a support layer over the etch stop layer comprises: Forming the sacrificial layer over the etch stop layer using an LPCVD process, a PECVD process, or a spin-on process; The support layer is formed over the sacrificial layer using the LPCVD process, the PECVD process, the PVD process, or the ALD process.
3. The method of claim 1, wherein the support layer is a material of SiN, siBN, siCN or SiON.
4. The method of claim 1, wherein the annealing the support layer after ion implantation comprises: and annealing the support layer after ion implantation by using a furnace tube annealing, rapid Thermal Processing (RTP) or laser annealing process, wherein the annealing temperature is 600-1100 ℃.
5. The method of claim 1, wherein the etch stop layer is of a material SiN, siBN, or SiCN.
6. The method of claim 1, wherein the hard mask layer is a composite layer of a dielectric and a disposable polymer, wherein the dielectric comprises at least one of SiO 2 , siN, polysilicon, and SiON, and the disposable polymer comprises at least one of photoresist photo resist, amorphous carbon layer ACL, and spin hard mask SOH.
7. The method of claim 1, wherein the semiconductor device is a dynamic memory, and further comprising patterning the hard mask layer, etching the stack using the patterned hard mask layer as a mask to form a capacitor hole and exposing the contact structure.
8. The method of claim 7, wherein the method further comprises: And forming a lower electrode, a capacitance dielectric layer and an upper electrode in the capacitance hole.
9. The method of claim 1, wherein the semiconductor substrate includes a buried channel transistor thereon, one of the source and drain regions of the transistor being in contact with a bit line and the other source and drain region being electrically connected to the contact structure.
10. A semiconductor device, the semiconductor device comprising: a semiconductor substrate; A contact structure on the semiconductor substrate; a capacitor electrically connected to the contact structure, the capacitor comprising a lower electrode, a capacitive dielectric layer, and an upper electrode; The lower electrode comprises a supporting structure, wherein the supporting structure is sequentially subjected to ion implantation and annealing treatment, the implanted ions comprise at least one of Ar, H, he, N, O, C, si and B ions, the supporting structure comprises at least one supporting layer, an Si-O network is cut off by utilizing ion collision in the supporting layer, and stress existing between the Si-O bonds is released.
11. The semiconductor device according to claim 10, wherein a material of the support layer is SiN, siBN, siCN or SiON.
12. The semiconductor device of claim 10, further comprising at least one or a combination of Ar, H, he ions in the support structure.

Description

Preparation method of semiconductor device and semiconductor device Technical Field The invention belongs to the technical field of semiconductor preparation, and particularly relates to a preparation method of a semiconductor device and the semiconductor device. Background In the fabrication of semiconductor devices, it is generally achieved by using a material having a large dielectric constant or enlarging the effective area of a capacitor electrode in order to increase the capacitance of the semiconductor device. In order to enlarge the effective area of the capacitor electrode, the height of the capacitor column structure is generally increased, and then the capacitor column structure is supported by the overlapped supporting layer, but the electrode is easily bent, cracked or lifted while the height is increased. In order to overcome the above problems in the prior art, the process window of the capacitor preparation process is reduced to prepare the supporting layer meeting the requirements of stress and compactness, that is, the process parameters in each process must be very strict, and although the phenomena of bending, cracking or lifting of the electrode can be slowed down, the process stability cannot be ensured due to the reduction of the process window. Disclosure of Invention Aiming at the problems existing in the prior art, the embodiment of the invention provides a preparation method of a semiconductor device and the semiconductor device, which are used for solving the technical problems that in the prior art, in order to avoid phenomena such as bending, cracking or lifting of a capacitor electrode and the like when the capacitance of the semiconductor device is increased by expanding the effective area of the capacitor electrode, process windows of various processes need to be strictly limited, so that the stability of the preparation process cannot be ensured, and the overall performance of the semiconductor device is affected. The invention provides a preparation method of a semiconductor device, which comprises the following steps: providing a semiconductor substrate, wherein a contact structure is formed on the semiconductor substrate, and the contact structure is electrically connected with a capacitor; Forming an etch stop layer over the contact structure; Sequentially forming a stack of a sacrificial layer and a supporting layer above the etching stop layer, wherein the sacrificial layer and the supporting layer both comprise at least one layer, and the positions of the sacrificial layer and the supporting layer are in cross stack; carrying out ion implantation on the support layer after forming the support layer each time, and carrying out annealing treatment on the support layer after ion implantation; a hard mask layer is formed over the topmost support layer. Optionally, the sequentially forming a stack of a sacrificial layer and a supporting layer above the etching stop layer includes: Forming the sacrificial layer over the etch stop layer using an LPCVD process, a PECVD process, or a spin-on process; And forming the supporting layer above the sacrificial layer by using the LPCVD process, the PECVD process, the PVD process or the ALD process, wherein the sacrificial layer and the supporting layer comprise at least one layer. Optionally, the material of the supporting layer is SiN, siBN, siCN or SiON. Optionally, the ion implanting the support layer after each forming of the support layer includes: At least one of Ar, H, he, N, O, C, si and B ions is implanted into the support layer formed at a time. Optionally, the annealing treatment of the support layer after the ion implantation includes: and annealing the support layer after ion implantation by using a furnace tube annealing, rapid Thermal Processing (RTP) or laser annealing process, wherein the annealing temperature is 600-1100 ℃. Optionally, the material of the etching stop layer is SiN, siBN or SiCN. Optionally, the hard mask layer is a composite layer formed by a dielectric and a disposable polymer, wherein the dielectric comprises at least one of SiO 2, siN, polysilicon and SiON, and the disposable polymer comprises at least one of photoresist photo resin, amorphous carbon layer ACL and spin hard mask SOH. Optionally, the semiconductor device is a dynamic memory, the method further comprises patterning the hard mask layer, and etching the stack layer to form a capacitor hole and expose the contact structure by using the patterned hard mask layer as a mask. Optionally, a lower electrode, a capacitance dielectric layer and an upper electrode are formed in the capacitance hole. Optionally, the semiconductor substrate includes a buried channel transistor thereon, one of the source and drain regions of the transistor is in contact with the bit line, and the other source and drain region is electrically connected with the contact structure. The present invention also provides a semiconductor device including: a semiconducto