CN-114446952-B - Semiconductor structure and forming method thereof

Abstract

A semiconductor structure comprises a dielectric wall, a blocking wall, a first channel layer and a first grid penetrating through the junction of a first region and a second region, wherein the blocking wall is positioned at one transverse end of the top of the dielectric wall, the projection of the blocking wall on a substrate is positioned in the projection of the dielectric wall on the substrate, and a second grid is positioned on the first grid and the dielectric wall at the side part of the blocking wall and is exposed out of the top of the blocking wall. In addition, because the blocking wall is positioned at the top of the dielectric wall, when the semiconductor structure works, the distance between the blocking wall and the channel is far, the blocking wall is not easy to generate stress on the channel, so that the migration rate of carriers in the channel is easy to meet the process requirement, and the electrical property of the semiconductor structure is improved.

Inventors

• JI SHILIANG
• XIAO XINGYU
• ZHANG HAIYANG

Assignees

• 中芯国际集成电路制造(上海)有限公司
• 中芯国际集成电路制造(北京)有限公司

Dates

Publication Date

20260505

Application Date

20201030

Claims (20)

1. 1. A semiconductor structure, comprising: providing a substrate, wherein the substrate comprises a first area and a second area; one or more first channel layers suspended on the substrate at intervals along the normal direction of the surface of the substrate; a first gate electrode on the substrate, the first gate electrode fully surrounding the first channel layer; a dielectric wall penetrating through the first channel layer and the first gate at the junction of the first region and the second region to be parallel to the surface of the substrate, and being transverse to the extending direction of the dielectric wall; A blocking wall located at one end of the dielectric wall in the transverse direction of the top of the dielectric wall, the blocking wall being offset from the top of the dielectric wall, the projection of the blocking wall onto the substrate being located in the projection of the dielectric wall onto the substrate; and the second grid electrode is positioned on the first grid electrode and the dielectric wall at the side part of the blocking wall and exposes the top part of the blocking wall.
2. 2. The semiconductor structure of claim 1, wherein the dielectric wall comprises laterally opposite first and second ends, the blocking wall being located at the first end of the dielectric wall laterally; The semiconductor structure further comprises a side wall material layer which is positioned on the side wall of the blocking wall close to the first end of the dielectric wall, and the bottom of the side wall material layer is in contact with the first grid electrode.
3. 3. The semiconductor structure of claim 2, wherein the sidewall material layer is further on top of the blocking wall.
4. 4. The semiconductor structure of claim 2, wherein a lateral dimension of the sidewall material layer is 1 nm to 5 nm.
5. 5. The semiconductor structure of claim 2, wherein the sidewall material layer comprises SiON, siBCN, siCN, carbon doped SiN, or oxygen doped SiN.
6. 6. The semiconductor structure of claim 1 or 2, wherein one sidewall of the blocking wall lateral direction is flush with one sidewall of the dielectric wall lateral direction in a direction perpendicular to the substrate surface normal.
7. 7. The semiconductor structure of claim 1 or 2, wherein the blocking wall has a lateral dimension of 14 nm to 20 nm.
8. 8. The semiconductor structure of claim 1, wherein the dielectric wall comprises laterally opposite first and second ends, the blocking wall being located at the first end of the dielectric wall laterally; the semiconductor structure further comprises a contact plug positioned at the top of the second grid electrode at the side of the second end away from the first end.
9. 9. The semiconductor structure of claim 1, wherein the substrate further comprises adjacent third and fourth regions; The semiconductor structure comprises one or more second channel layers, one or more first grid electrodes and one or more second grid electrodes, wherein the second channel layers are suspended on the substrate at intervals along the normal direction of the surface of the substrate, and the first grid electrodes also completely surround the second channel layers; The dielectric wall penetrates through the second channel layer and the first grid at the junction of the third region and the fourth region.
10. 10. A method of forming a semiconductor structure, comprising: Providing a substrate, wherein the substrate comprises a substrate, one or more first channel layers, a first grid structure, an initial dielectric wall, a second channel layer, a first grid structure, a second grid structure, a first dielectric wall, a second dielectric wall and a second dielectric layer, wherein the first region and the second region are adjacent; Etching part of the thickness of the first gate structure to form a second gate structure which completely surrounds the first channel layer and exposes part of the side wall of the initial dielectric wall; Etching one end of the initial dielectric wall, which is parallel to the surface of the substrate and perpendicular to the extending direction of the initial dielectric wall, to expose the second gate structure, wherein the remaining initial dielectric wall, which is exposed from the second gate structure, is used as a blocking wall, and the remaining initial dielectric wall, which is positioned in the second gate structure, is used as a dielectric wall; And forming a third gate structure on the second gate structure, wherein the third gate structure exposes the top of the blocking wall.
11. 11. The method of forming a semiconductor structure as claimed in claim 10, further comprising etching a portion of the thickness of the first gate structure to form a second gate structure, and conformally covering a sidewall material layer on the initial dielectric wall and the exposed second gate structure before etching to expose a lateral end of the initial dielectric wall of the second gate structure; And etching to expose one transverse end of the initial dielectric wall of the second grid structure, and etching the side wall material layer on the surface of the second grid structure and the side wall material layer on one transverse side wall of the initial dielectric wall in the step of forming a blocking wall, wherein the remaining initial dielectric wall and the side wall material layer of the second grid structure are exposed to serve as the blocking wall.
12. 12. The method of claim 11, wherein the sidewall material layer is formed by an atomic layer deposition process or a chemical vapor deposition process.
13. 13. The method of claim 11, wherein in the step of forming the sidewall material layer, a thickness of the sidewall material layer is 1 nm to 5 nm.
14. 14. The method of claim 11, wherein the sidewall material layer comprises SiON, siBCN, siCN, carbon-doped SiN, or oxygen-doped SiN.
15. 15. The method of forming a semiconductor structure of claim 10 or 11, wherein etching to expose a lateral end of the initial dielectric wall of the second gate structure, the step of forming a blocking wall comprises: forming a mask layer on the initial dielectric wall and the second grid structure, wherein the mask layer exposes one transverse end of the initial dielectric wall; etching the initial dielectric wall by taking the mask layer as a mask, and exposing the rest of the initial dielectric wall of the second grid structure as the blocking wall; the method for forming the semiconductor structure further comprises the step of removing the mask layer after the blocking wall is formed.
16. 16. The method of claim 15, wherein the masking layer is used as a mask, and an anisotropic dry etching process is used to etch and expose a lateral end of the initial dielectric wall of the second gate structure, and expose the remaining initial dielectric wall of the second gate structure as the blocking wall.
17. 17. The method of forming a semiconductor structure as recited in claim 16 wherein said blocking wall forming step further comprises etching a lateral end of said initial dielectric wall exposing said second gate structure, and then performing a lateral trimming process on a sidewall of said initial dielectric wall exposing said second gate structure to expose the remaining initial dielectric wall of said second gate structure as said blocking wall.
18. 18. The method of claim 17, wherein the sidewalls of the initial dielectric wall exposed by the second gate structure are trimmed laterally using an isotropic dry etch process.
19. 19. The method of forming a semiconductor structure according to claim 10 or 11, wherein in the step of forming the blocking wall, a lateral dimension of the blocking wall is 14 nm to 20 nm.
20. 20. The method of forming a semiconductor structure of claim 10, wherein forming a third gate structure over the second gate structure comprises: Forming a gate material layer on the second gate structure and the blocking wall; And removing the gate material layer higher than the blocking wall, and taking the rest gate material layer as a third gate structure.

Description

Semiconductor structure and forming method thereof Technical Field Embodiments of the present disclosure relate to semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same. Background In semiconductor manufacturing, with the trend of very large scale integrated circuits, the feature size of integrated circuits is continuously reduced, and in order to adapt to smaller feature sizes, the channel length of Metal-Oxide-semiconductor field effect transistors (MOSFETs) is also continuously shortened. Accordingly, to better accommodate the demand for device scaling, semiconductor processes are increasingly beginning to transition from planar transistors to three-dimensional transistors with higher power, such as Gate-all-around (GAA) transistors. In the fully-enclosed metal gate transistor, the gate encloses the region where the channel is located from the periphery, and compared with a planar transistor, the gate of the fully-enclosed metal gate transistor has stronger control capability on the channel and can better inhibit the short channel effect. With the development of semiconductor processes, to increase the integration of semiconductor structures and reduce the spacing between transistors, forksheet transistors, which are the option after FinFET and fully-surrounding transistors, have been proposed, which are separated by dielectric walls (wall) due to complex double sided fin structures. When the Forksheet structure with higher integration level works, how to reduce the influence of the back-end structure on the carrier migration rate in the channel, so that the carrier migration rate meets the working requirement, and is important to improving the Forksheet performance. Disclosure of Invention The embodiment of the invention solves the problem of providing a semiconductor structure and a forming method thereof, which can meet the high integration level of the semiconductor structure, simultaneously ensure that the migration rate of carriers of a channel meets the process requirement and optimize the electrical property of the semiconductor structure. To solve the problems, the embodiment of the invention provides a semiconductor structure, which comprises a substrate, one or more first channel layers, a first grid, a dielectric wall, a blocking wall, a second grid, a blocking wall and a blocking wall, wherein the substrate comprises a first area and a second area, one or more first channel layers are suspended on the substrate at intervals along the normal direction of the surface of the substrate, the first grid is positioned on the substrate, the first grid completely surrounds the first channel layers, the dielectric wall penetrates through the first channel layers and the first grid at the junction of the first area and the second area to be parallel to the surface of the substrate and transversely to the extending direction of the dielectric wall, the blocking wall is positioned at one transverse end of the top of the dielectric wall, the projection of the blocking wall on the substrate is positioned in the projection of the dielectric wall on the substrate, and the first grid and the dielectric wall are positioned at the side of the blocking wall and the top of the blocking wall is exposed. Correspondingly, the embodiment of the invention also provides a method for forming the semiconductor structure, which comprises the steps of providing a substrate, wherein the substrate comprises a first area and a second area which are adjacent, the substrate comprises a substrate, one or more first channel layers which are suspended on the substrate at intervals along the normal direction of the surface of the substrate, a first grid structure which completely surrounds the first channel layer, an initial dielectric wall which penetrates through the first channel layer and the first grid structure at the junction of the first area and the second area, etching a part of the first grid structure with partial thickness to form a second grid structure which completely surrounds the first channel layer and exposes part of the side wall of the initial dielectric wall, etching a part of the thickness of the transverse end of the initial dielectric wall which exposes the second grid structure to serve as a blocking wall, remaining dielectric walls which are located in the second grid structure to serve as a blocking wall, and forming a third grid structure on the top of the dielectric wall which is exposed. Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages: In the semiconductor structure provided by the embodiment of the invention, the dielectric wall penetrates through the first channel layer and the first grid at the junction of the first region and the second region, the blocking wall is positioned at one transverse end of the top of the dielectric wall, the projection of the blocking wall on t