CN-114464218-B - Power management for memory devices

Abstract

The present disclosure is directed to power management for memory devices. For example, a memory device may include one or more memory dies and may be configured to operate using a first supply voltage and a second supply voltage. The first supply voltage may be associated with a first defined voltage range and the second supply voltage may be associated with a second defined voltage range. The memory device may include a power management integrated circuit, PMIC, coupled with the one or more memory dies and providing the supply voltage to the one or more memory dies. The PMIC may be configured to provide a first voltage within the first defined voltage range as the first supply voltage and a second voltage outside the second defined voltage range as the second supply voltage to the one or more memory dies.

Inventors

• J.S. Rehmael
• G L h. Howe
• M. S. Wisconsin
• E. J. Steffe

Assignees

• 美光科技公司

Dates

Publication Date

20260512

Application Date

20211104

Priority Date

20201110

Claims (19)

1. 1. A system, comprising: A memory die configured to exchange signaling with a host device according to a memory standard and to operate using a first supply voltage and a second supply voltage, wherein the first supply voltage is associated with a first defined voltage range specified by the memory standard and the second supply voltage is associated with a second defined voltage range specified by the memory standard, and A power management integrated circuit PMIC coupled with the memory die and configured to: Reading a first value stored in a register and a second value stored in the register, wherein the first value indicates a first voltage of the first supply voltage and the second value indicates a second voltage of the second supply voltage; After reading the first value and the second value, providing the first voltage within the first defined voltage range specified by the memory standard as the first supply voltage to the memory die based at least in part on reading the first value stored in the register, and The second voltage that is outside the second defined voltage range specified by the memory standard is provided to the memory die as the second supply voltage concurrently with providing the first voltage based at least in part on reading the second value stored in the register.
2. 2. The system of claim 1, wherein the PMIC is further configured to: The second voltage that is outside the second defined voltage range is identified during initialization of the system, wherein providing the second voltage is based at least in part on the identifying.
3. 3. The system of claim 2, further comprising: The register is coupled with or included in the PMIC and configured to store the first value indicative of the first voltage within the first defined voltage range and the second value indicative of the second voltage outside the second defined voltage range, wherein the identifying is based at least in part on the register storing the first value indicative of the first voltage and the second value indicative of the second voltage.
4. 4. A system according to claim 3, wherein: the memory die is configured to couple with the host device, and The first value and the second value are not changeable by the host device.
5. 5. The system of claim 1, wherein the PMIC is configured to provide the second voltage based at least in part on the memory die meeting a performance threshold when using the second voltage as the second supply voltage.
6. 6. The system of claim 1, wherein: A dual in-line memory module DIMM includes the PMIC, the memory die, and one or more additional memory dies each configured to operate using the first supply voltage and the second supply voltage; the memory die and the one or more additional memory dies each comprise dynamic random access memory DRAM memory cells, and The PMIC is further configured to: providing the first voltage within the first defined voltage range as the first supply voltage to each of the one or more additional memory dies, and The second voltage that is outside the second defined voltage range is provided as the second supply voltage to each of the one or more additional memory dies.
7. 7. The system of claim 1, wherein the second voltage is lower than the second defined voltage range.
8. 8. The system of claim 1, wherein the second voltage is higher than the second defined voltage range.
9. 9. A method, comprising: Reading, by a power management integrated circuit PMIC coupled with a memory die, a first value stored in a register and a second value stored in the register, the memory die configured to exchange signaling with a host device according to a memory standard, wherein the first value indicates a first voltage of a first supply voltage and the second value indicates a second voltage of a second supply voltage; After reading the first value and the second value, generating, using the PMIC, the first voltage within a first defined voltage range specified by the memory standard corresponding to the first supply voltage of the memory die based at least in part on reading the first value stored in the register; Generating, using the PMIC, a second voltage outside a second defined voltage range specified by the memory standard corresponding to a second supply voltage of the memory die based at least in part on reading the second value stored in the register, and The memory die is operated simultaneously using the first voltage as the first supply voltage and the second voltage as the second supply voltage.
10. 10. The method of claim 9, further comprising: the one or more additional memory dies coupled with the PMIC are operated using the first voltage and the second voltage as one or more respective first supply voltages and one or more second supply voltages for the one or more additional memory dies.
11. 11. The method of claim 9, wherein generating the second voltage further comprises: The second voltage is identified during an initialization procedure performed prior to operating the memory die.
12. 12. The method of claim 9, wherein the second voltage is lower than the second defined voltage range.
13. 13. The method of claim 9, wherein the second voltage is higher than the second defined voltage range.
14. 14. The method as recited in claim 11, further comprising: the first value indicative of the first voltage within the first defined voltage range and the second value indicative of the second voltage outside the second defined voltage range are stored into the register coupled with or included in the PMIC, wherein the identifying is based at least in part on storing the first value indicative of the first voltage and the second value indicative of the second voltage into the register.
15. 15. The method according to claim 14, wherein: the memory die is configured to couple with the host device, and The first value and the second value are not changeable by the host device.
16. 16. The method of claim 9, wherein generating the second voltage using the PMIC is based at least in part on the memory die meeting a performance threshold when using the second voltage as the second supply voltage.
17. 17. A memory device, comprising: a memory die configured to exchange signaling with a host device according to a memory standard, and One or more controllers coupled with the memory die, wherein the one or more controllers are configured to cause the memory device to: Reading, by a power management integrated circuit PMIC coupled with the memory die, a first value stored in a register and a second value stored in the register, wherein the first value is indicative of a first voltage of a first supply voltage and the second value is indicative of a second voltage of a second supply voltage; After reading the first value and the second value, generating, using the PMIC, the first voltage within a first defined voltage range specified by the memory standard corresponding to the first supply voltage of the memory die based at least in part on reading the first value stored in the register; Generating, using the PMIC, the second voltage outside a second defined voltage range specified by the memory standard corresponding to the second supply voltage of the memory die based at least in part on reading the second value stored in the register, and The memory die is operated simultaneously using the first voltage as the first supply voltage and the second voltage as the second supply voltage.
18. 18. The memory device of claim 17, wherein the one or more controllers are further configured to cause the memory device to: The one or more additional memory dies coupled with the PMIC are operated using the first voltage and the second voltage as one or more respective first supply voltages and one or more second supply voltages for one or more additional memory dies.
19. 19. The memory device of claim 17, wherein to generate the second voltage, the one or more controllers are further configured to cause the memory device to: The second voltage is identified during an initialization procedure performed prior to operating the memory die.

Description

Power management for memory devices Cross reference This patent application claims Lei Meier (Rehmeyer) priority to U.S. patent application No. 17/094,579 entitled "power management for memory devices (POWER MANAGEMENT FOR A MEMORY DEVICE)" filed 11/10/2020, which is assigned to the present assignee and is expressly incorporated herein by reference in its entirety. Technical Field The technical field relates to power management for memory devices. Background Memory devices are widely used to store information in a variety of electronic devices, such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming memory cells within a memory device to various states. For example, a binary memory cell can be programmed to one of two support states, often indicated by a logic 1 or a logic 0. In some examples, a single memory cell may support more than two states, any of which may be stored. To access the stored information, the component may read or sense at least one stored state in the memory device. To store information, the component may write or program a state in the memory device. There are various types of memory devices and memory cells including magnetic hard disks, random Access Memory (RAM), read Only Memory (ROM), dynamic RAM (DRAM), static RAM, synchronous Dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase Change Memory (PCM), self-selected memory, chalcogenide memory technology, and others. The memory cells may be volatile or nonvolatile. Nonvolatile memory such as FeRAM can maintain its stored logic state for a long period of time even if no external power source is present. Volatile memory devices, such as DRAMs, may lose their stored state when disconnected from an external power source. Disclosure of Invention A system is described. The system may include a memory die configured to operate using a first supply voltage and a second supply voltage, wherein the first supply voltage is associated with a first defined voltage range and the second supply voltage is associated with a second defined voltage range, and a Power Management Integrated Circuit (PMIC) coupled with the memory die and configured to provide a first voltage within the first defined voltage range as the first supply voltage to the memory die, and a second voltage outside the second defined voltage range as the second supply voltage to the memory die. A method is described. The method may include generating, using a PMIC coupled with a memory die, a first voltage that is within a first defined voltage range corresponding to a first supply voltage of the memory die, generating, using the PMIC, a second voltage that is outside a second defined voltage range corresponding to a second supply voltage of the memory die, and operating the memory die using the first voltage as the first supply voltage and the second voltage as the second supply voltage. Another method is described. The method may include testing one or more performance characteristics of each memory die in a set of memory dies when supplied with a second voltage, wherein the second voltage is different from a first voltage corresponding to a default supply voltage for each memory die in the set of memory dies, identifying a subset of memory dies within the set of memory dies that each meet a performance threshold when supplied with the second voltage based at least in part on the testing, assembling a memory device to include a PMIC and the subset of memory dies based at least in part on the identifying the subset of memory dies, and setting an output voltage of the PMIC to be equal to the second voltage, wherein the PMIC is configured to supply the second voltage to the subset of memory dies during operation of the memory device based at least in part on the output voltage of the PMIC being set to the second voltage. Drawings 1-3 Illustrate examples of systems supporting power management for memory devices according to examples disclosed herein. Fig. 4 illustrates an example of a process flow supporting power management for a memory device in accordance with an example disclosed herein. Fig. 5 illustrates a block diagram of a system supporting power management for a memory device in accordance with aspects of the disclosure. Fig. 6 and 7 show flowcharts illustrating one or more methods of supporting power management for a memory device according to examples disclosed herein. Detailed Description The memory device may receive one or more supply voltages to enable the memory device to provide voltages to various components of the memory device. In some cases, a default value or range of supply voltages may be defined (e.g., a range may correspond to a value plus or minus some tolerance). For example, a default value or range of supply voltages may be defined in a standard applicable to a memory device, such as a joint electron device engineering design