CN-114496001-B - Reverse bias optimization

Abstract

The present application relates to reverse bias optimization. An apparatus, such as an electronic device, may include a first substrate region and a second substrate region. The apparatus may also include a voltage generator disposed on the first substrate region and including an output terminal coupled with a conductive path. The apparatus may also include a set of clamping circuits disposed on the second substrate region. The set of clamping circuits may be configured to selectively couple the conductive path with a voltage supply.

Inventors

• M. Brox
• SUGIMOTO SATOSHI
• E. Kavrella Bernal
• J. Portgiesel
• S. Piatkovsky

Assignees

• 美光科技公司

Dates

Publication Date

20260505

Application Date

20211028

Priority Date

20201112

Claims (20)

1. 1. An apparatus for reverse biasing, comprising: A first substrate region and a second substrate region; A voltage generator disposed on the first substrate region and including an output terminal coupled with the conductive path; A plurality of clamping circuits disposed on the second substrate region, each of the plurality of clamping circuits being configurable to couple the conductive path with a voltage supply, and A controller coupled with the voltage generator and the plurality of clamp circuits, the controller configured to independently enable and disable the voltage generator and enable and disable the plurality of clamp circuits.
2. 2. The apparatus of claim 1, further comprising: a clamp circuit is disposed on the first substrate region and coupled with the voltage generator.
3. 3. The apparatus of claim 1, wherein the controller is configured to enable or disable the voltage generator and enable or disable the plurality of clamp circuits based at least in part on an operating mode of the apparatus.
4. 4. The apparatus of claim 1, further comprising: A mode register configured to indicate an operating mode of the apparatus, wherein the controller is configured to enable or disable the voltage generator and enable or disable the plurality of clamp circuits based at least in part on the operating mode indicated by the mode register.
5. 5. The apparatus of claim 1, further comprising: A fuse configured to indicate a switching property of a transistor in the apparatus, wherein the controller is configured to enable or disable the voltage generator and the plurality of clamp circuits based at least in part on the switching property.
6. 6. The apparatus of claim 1, further comprising: A second conductive path coupled with a second output terminal of the voltage generator, wherein the plurality of clamping circuits are configurable to couple the second conductive path with a second voltage supply.
7. 7. The apparatus of claim 1, further comprising: A second voltage generator is disposed on the first substrate region and includes an output terminal coupled with the conductive path.
8. 8. The apparatus of claim 7, wherein the voltage generator and the second voltage generator are on opposite sides of the second substrate region.
9. 9. The apparatus of claim 1, wherein the conductive path spans an entire length of the second substrate region and the plurality of clamping circuits are distributed along the conductive path.
10. 10. The apparatus of claim 1, wherein the second substrate region is at least partially surrounded on both sides by the first substrate region.
11. 11. The apparatus of claim 1, wherein the second substrate region is subject to a set of constraints for placement of one or more wires or components, the first substrate region not following the set of constraints.
12. 12. The apparatus of claim 11, wherein the second substrate region is a peripheral substrate region comprising a matrix sub-region subject to the set of constraints, and wherein each clamp circuit is disposed on a respective sub-region of the matrix sub-region.
13. 13. An apparatus for reverse biasing, comprising: A first substrate region and a second substrate region, the second substrate region configured for components smaller than a threshold size; A voltage generator disposed on the first substrate region and including an output terminal coupled with a conductive path, the voltage generator being greater than the threshold size; A plurality of clamping circuits disposed on the second substrate region, each configurable to couple the conductive path with a voltage supply and each less than the threshold size, and A second conductive path coupled with a second output terminal of the voltage generator, wherein the plurality of clamping circuits are configurable to couple the second conductive path with a second voltage supply, and wherein each clamping circuit of the plurality of clamping circuits comprises: A first transistor coupled with the conductive path and the voltage supply, and A second transistor is coupled with the second conductive path and the second voltage supply.
14. 14. An apparatus for reverse biasing, comprising: A first substrate region and a second substrate region; A voltage generator disposed on the first substrate region and configured to generate a first voltage on a first conductive path and a second voltage on a second conductive path, the first and second voltages being used to bias transistors in at least the second substrate region, an A plurality of clamping circuits disposed on the second substrate region and coupled with the voltage generator, wherein each clamping circuit of the plurality of clamping circuits is configured to provide a third voltage to the first conductive path and a fourth voltage to the second conductive path, the third and fourth voltages being used to bias the transistor, wherein the first voltage is higher than the third voltage and the second voltage is lower than the fourth voltage.
15. 15. The apparatus of claim 14, wherein the first conductive path is coupled with a first type of transistor and the second conductive path is coupled with a second type of transistor.
16. 16. The apparatus of claim 15, wherein the transistors of the first type comprise p-type transistors and the transistors of the second type comprise n-type transistors.
17. 17. The apparatus of claim 14, further comprising: a controller configured to individually enable the voltage generator during a first duration and to individually enable the plurality of clamp circuits during a second duration, the second duration not overlapping the first duration.
18. 18. The apparatus of claim 17, wherein the controller is configured to: The voltage generator is enabled and the plurality of clamp circuits are disabled based at least in part on determining that the apparatus is in a test mode.
19. 19. The apparatus of claim 17, wherein the controller is configured to: the plurality of clamp circuits are enabled and the voltage generator is disabled based at least in part on determining that the transistor has a switching speed that is slower than a threshold switching speed.
20. 20. The apparatus of claim 14, further comprising: a controller configured to select a first bias mode or a second bias mode based at least in part on a switching nature of the transistor or an operating mode of the apparatus, wherein the controller is configured to enable or disable the voltage generator and enable or disable the plurality of clamp circuits based at least in part on the selected bias mode.

Description

Reverse bias optimization Cross reference to This patent application claims priority to U.S. patent application Ser. No. 17/096,225 entitled "reverse bias optimization (BACK-BIAS OPTIMIZATION)" to Brorocs (Brox) et al, 11/12, 2020, which is assigned to the assignee hereof and is expressly incorporated herein by reference in its entirety. Technical Field The technical field relates to reverse bias optimization. Background Memory devices are widely used to store information in a variety of electronic devices, such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming memory cells within a memory device to various states. For example, a binary memory cell may be programmed to one of two supported states, typically represented by a logic 1 or a logic 0. In some examples, a single memory cell may support more than two states, any of which may be stored. To access the stored information, the component may read or sense at least one storage state in the memory device. To store information, components may write or program states in a memory device. There are various types of memory devices and memory cells including magnetic hard disks, random Access Memory (RAM), read Only Memory (ROM), dynamic RAM (DRAM), synchronous Dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase Change Memory (PCM), self-selected memory, chalcogenide memory technology, and others. The memory cells may be volatile or nonvolatile. Nonvolatile memory (e.g., feRAM) may maintain its stored logic state for extended periods of time even in the absence of external power. Volatile memory devices, such as DRAMs, may lose their memory state when disconnected from an external power source. Disclosure of Invention An apparatus is described. The apparatus may include a first substrate region and a second substrate region, a voltage generator disposed on the first substrate region and including an output terminal coupled with a conductive path, and a plurality of clamping circuits disposed on the second substrate region, each of the plurality of clamping circuits being configurable to couple the conductive path with a voltage supply. An apparatus is described. The apparatus may include a first substrate region and a second substrate region, a voltage generator disposed on the first substrate region and configured to generate a first voltage on a first conductive path and a second voltage on a second conductive path, the first and second voltages for biasing transistors in at least the second substrate region, and a plurality of clamping circuits disposed on the second substrate region and coupled with the voltage generator, wherein each clamping circuit of the plurality of clamping circuits is configured to provide a third voltage to the first conductive path and a fourth voltage to the second conductive path, the third and fourth voltages for biasing the transistors. An apparatus is described. The apparatus may include a first voltage generator disposed on a first substrate region, the first voltage generator configured to generate a first voltage and a second voltage for biasing a transistor in a second substrate region, a second voltage generator disposed on the first substrate region, the second voltage generator configured to generate the first voltage and the second voltage for biasing the transistor, a clamp circuit disposed on the second substrate region at least partially surrounded by the first substrate region, and configurable to provide a third voltage and a fourth voltage for biasing the transistor. Drawings FIG. 1 illustrates an example of a system supporting reverse bias optimization in accordance with examples disclosed herein. FIG. 2 illustrates an example of a device supporting reverse bias optimization in accordance with examples disclosed herein. Fig. 3A and 3B illustrate examples of process flows supporting reverse bias optimization in accordance with examples disclosed herein. Detailed Description Devices such as electronic devices may apply bias voltages to various electronic components to prevent or mitigate deleterious electrical phenomena. For example, the device may apply a bias voltage to the body (or "back side") of the transistor to mitigate current leakage. This process may be referred to as reverse biasing. Devices employing reverse bias may include a bias circuit including a voltage generator and a clamp circuit that may each provide a different reverse bias voltage for different scenarios. Because of its size and complexity, the bias circuit may be disposed on a substrate area (e.g., a fully custom area) of the device that is relatively unconstrained by component placement. The conductive path may couple the bias circuit with various transistors, some of which may be disposed on another substrate region (e.g., a semi-custom region) subject to relatively restrictive element placement constraints