CN-114496009-B - Word line characteristic monitor for memory devices and associated methods and systems

Abstract

The present disclosure relates to a wordline characteristic monitor for a memory device and associated methods and systems. In one embodiment, the memory device includes a memory array including word lines (e.g., local word lines) and word line drivers coupled to the word lines. When the memory device activates the word line driver, the memory device may generate a diagnostic signal in response to the word line voltage reaching a threshold. Further, the memory device may generate a reference signal to compare the diagnostic signal to the reference signal. In some cases, if the diagnostic signal indicates a sign of degradation of a word line characteristic, the memory device may generate an alert signal based on comparing the diagnostic signal to the reference signal. The memory device may implement certain precautions and/or countermeasures upon detection of the symptom.

Inventors

• M. A. Blaise
• R. J. Rooney

Assignees

• 美光科技公司

Dates

Publication Date

20260512

Application Date

20211025

Priority Date

20201027

Claims (20)

1. 1. A memory apparatus, comprising: A memory array; A word line driver coupled to word lines of the memory array, and Peripheral circuitry coupled with the memory array and the word line driver, the peripheral circuitry configured to: Activating the word line driver; transmitting a first signal in response to the word line voltage reaching a threshold value, and A second signal is transmitted based at least in part on comparing the first signal to a reference, Wherein the first signal is a diagnostic signal, the second signal is an alarm signal, and the reference includes one or more predetermined parameters having a reference duration, a reference transition of a voltage waveform, or both.
2. 2. The memory apparatus of claim 1, wherein the peripheral circuitry is configured to activate the word line driver in response to: receiving an access command directed to the word line from a host device coupled with the memory device; Initiate a refresh operation directed to the word line, or An error checking and cleaning ECS operation directed to the word line is initiated.
3. 3. The memory apparatus of claim 1, further comprising: a reference component coupled with the peripheral circuitry, the reference component configured to generate the reference.
4. 4. The memory apparatus of claim 1, wherein the reference includes the reference duration and the peripheral circuitry is configured to: Upon comparing the first signal to the reference, determining that a duration associated with the first signal is greater than the reference duration, wherein the duration corresponds to a period of time between activating the word line driver and the word line voltage reaching the threshold.
5. 5. The memory apparatus of claim 1, wherein the reference includes the reference transition of the voltage waveform, and the peripheral circuitry is configured to: Upon comparing the first signal to the reference, determining that a transition of the first signal lags the reference transition, wherein the transition of the first signal is associated with the word line voltage reaching the threshold.
6. 6. The memory apparatus of claim 1, wherein the memory array is configured to include a global word line and a plurality of local word lines coupled with the global word line, and wherein: the word line is a first local word line of the plurality of local word lines; The word line driver is a first word line driver configured to drive the first local word line from a first end of the first local word line, and A first word line voltage monitoring component of the peripheral circuitry is coupled to a second end of the first local word line opposite the first end, the first word line voltage monitoring component configured to generate the first signal.
7. 7. The memory apparatus of claim 6, wherein the reference includes the reference duration and the peripheral circuitry is configured to: Determining that a duration associated with the first signal is greater than the reference duration, wherein the duration corresponds to a period of time between activating the first word line driver and the voltage of the first local word line reaching the threshold value, and The duration is determined to be greater than any of the durations associated with other local word lines of the plurality of local word lines.
8. 8. The memory apparatus of claim 6, wherein the reference includes the reference transition of the voltage waveform, and the peripheral circuitry is configured to: determining that a transition of the first signal lags the reference transition, wherein the transition of the first signal is associated with a voltage of the first local word line reaching the threshold value, and It is determined that the transition occurs later than any of the transitions associated with other local word lines of the plurality of local word lines.
9. 9. The memory apparatus of claim 1, wherein the peripheral circuitry is further configured to: Storing an address associated with the word line in a register of the memory device in response to generating the second signal, and The address is replaced with a different address of the memory array in response to receiving an access command including the address from a host device coupled with the memory apparatus.
10. 10. The memory apparatus of claim 1, wherein the peripheral circuitry is further configured to: Storing an address associated with the word line in a register of the memory device in response to generating the second signal, and In response to executing an access command that includes the address, it is determined whether an error checking and correction ECC engine of the memory device detects at least one error in data associated with the address.
11. 11. The memory apparatus of claim 1, wherein the peripheral circuitry is further configured to: Storing an address associated with the word line in a register of the memory device in response to generating the second signal, and The second signal is sent to a host device coupled with the memory device, the second signal including the address associated with the word line.
12. 12. A method performed by an apparatus comprising a memory array, comprising: activating a word line driver coupled to a word line of the memory array; transmitting a first signal in response to the word line voltage reaching a threshold value, and A second signal is transmitted based at least in part on comparing the first signal to a reference, Wherein the first signal is a diagnostic signal, the second signal is an alarm signal, and the reference includes one or more predetermined parameters having a reference duration, a reference transition of a voltage waveform, or both.
13. 13. The method of claim 12, wherein activating the word line driver is in response to: receiving an access command directed to the word line from a host device coupled with the apparatus including the memory array; Initiate a refresh operation directed to the word line, or An error checking and cleaning ECS operation directed to the word line is initiated.
14. 14. The method of claim 12, wherein the reference includes the reference transition of the voltage waveform, and comparing the first signal to the reference further comprises: a transition of the first signal is determined to lag the reference transition, wherein the transition of the first signal is associated with the word line voltage reaching the threshold.
15. 15. The method of claim 12, wherein the reference includes the reference duration, and comparing the first signal to the reference further comprises: A duration associated with the first signal is determined to be greater than the reference duration, wherein the duration corresponds to a period of time between activating the word line driver and the word line voltage reaching the threshold.
16. 16. The method of claim 12, wherein the memory array is configured to include a global word line and a plurality of local word lines coupled with the global word line, and wherein: the word line is a first local word line of the plurality of local word lines; The word line driver is a first word line driver configured to drive the first local word line from a first end of the first local word line, and A first word line voltage monitoring component is coupled to a second end of the first local word line opposite the first end.
17. 17. The method as recited in claim 12, further comprising: storing an address associated with the word line in a register of the device including the memory array in response to generating the second signal, and At least one of the following is performed: Replacing the address with a different address in response to receiving an access command including the address from a host device coupled with the apparatus; Determining whether an error checking and correcting ECC engine of the apparatus detects at least one error in data associated with the address in response to executing an access command including the address, or The second signal is sent to the host device, the second signal including the address associated with the word line.
18. 18. A system for memory operation, comprising: Host device and method for manufacturing the same A semiconductor device coupled with the host device, the semiconductor device comprising: A memory array; A word line driver coupled to word lines of the memory array, and Peripheral circuitry coupled with the memory array and the word line driver, the peripheral circuitry configured to: Activating the word line driver; Transmitting a first signal in response to a voltage of the word line reaching a threshold; transmitting a second signal based at least in part on comparing the first signal to a reference, and Sending the second signal to the host device, the second signal including an address associated with the word line, Wherein the first signal is a diagnostic signal, the second signal is an alarm signal, and the reference includes one or more predetermined parameters having a reference duration, a reference transition of a voltage waveform, or both.
19. 19. The system of claim 18, wherein the host device is configured to: transmitting an access command directed to the address in response to receiving the second signal including the address, and In response to executing the access command, monitoring an error checking and correction ECC engine of the semiconductor device for at least one error in data associated with the address.
20. 20. The system of claim 18, wherein in response to receiving the second signal including the address, the host device is configured to perform at least one of: disabling the address when generating an access command directed to the semiconductor device; Retire a portion of the memory array that includes the address, or Access operations directed to the semiconductor device are prohibited.

Description

Word line characteristic monitor for memory devices and associated methods and systems Technical Field The present disclosure relates generally to semiconductor memory devices, and more particularly to word line characteristic monitors for memory devices and associated methods and systems. Background Memory devices are widely used to store information related to various electronic devices, such as computers, wireless communication devices, cameras, digital displays, and the like. Memory devices are often provided as internal semiconductor integrated circuits and/or external removable devices in a computer or other electronic device. There are many different types of memory, including volatile and non-volatile memory. Volatile memory, including Random Access Memory (RAM), static Random Access Memory (SRAM), dynamic Random Access Memory (DRAM), synchronous Dynamic Random Access Memory (SDRAM), and the like, requires an external power source to maintain their data. In contrast, non-volatile memory can retain its stored data even without external power. Nonvolatile memory may be used in a variety of technologies, including flash memory (e.g., NAND and NOR), phase Change Memory (PCM), ferroelectric random access memory (FeRAM), resistive Random Access Memory (RRAM), and Magnetic Random Access Memory (MRAM), among others. Improving memory devices may generally include increasing memory cell density, increasing read/write speed or otherwise reducing operation latency, increasing reliability, increasing data retention, reducing power consumption, or reducing manufacturing costs, among other metrics. Disclosure of Invention In one aspect, this disclosure relates to an apparatus comprising a memory array, a word line driver coupled to a word line of the memory array, and peripheral circuitry coupled with the memory array and the word line driver, the peripheral circuitry configured to activate the word line driver, transmit a first signal in response to a voltage of the word line reaching a threshold, and transmit a second signal based at least in part on comparing the first signal to a reference. In another aspect, the disclosure is directed to a method that includes activating a word line driver coupled to a word line of a memory array, transmitting a first signal in response to a voltage of the word line reaching a threshold, and transmitting a second signal based at least in part on comparing the first signal to a reference. In another aspect, this disclosure is directed to a system comprising a host device, and a semiconductor device coupled with the host device, the semiconductor device including a memory array, a word line driver coupled to a word line of the memory array, and peripheral circuitry coupled with the memory array and the word line driver, the peripheral circuitry configured to activate the word line driver, transmit a first signal in response to a voltage of the word line reaching a threshold, transmit a second signal based at least in part on comparing the first signal to a reference, and send the second signal to the host device, the second signal including an address associated with the word line. Drawings The present disclosure will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the disclosure. The components in the drawings are not necessarily to scale. Emphasis instead being placed upon clearly illustrating the principles of the present technology. FIG. 1 is a block diagram schematically illustrating a memory device in accordance with an embodiment of the present technique. FIG. 2 is a block diagram illustrating a wordline characteristic monitor of a memory device in accordance with an embodiment of the present technique. FIG. 3 illustrates a timing diagram associated with a word line characteristic monitor of a memory device in accordance with an embodiment of the present technique. FIG. 4 is a block diagram schematically illustrating a word line characteristic monitor of a memory device in accordance with an embodiment of the present technique. FIG. 5 is a block diagram of a system having a memory device configured in accordance with an embodiment of the present technology. FIG. 6 is a flow chart illustrating a method of operating a memory device in accordance with an embodiment of the present technique. Detailed Description As memory cells expand to increase the memory density and storage capacity of memory devices, meeting various reliability criteria for memory devices becomes increasingly challenging. Error Checking and Correction (ECC) functions may help circumvent certain reliability issues, but increase the overhead of overall memory system bandwidth and cost. As such, memory systems may reduce ECC robustness, which in turn tends to increase memory device failures in the field. Furthermore, challenges associated with forming word lines of a memory array in current state-of-the-art semiconductor fabrica