CN-114496815-B - SiP packaging design method of IPC monitoring chip

Abstract

The invention provides a SiP packaging design method of an IPC monitoring chip, which fully utilizes the layout of die in the package and adjusts the signal distribution sequence of a main control DIE DDR PHY interface, omits RDL, can reduce the production and manufacturing cost of the IPC monitoring chip, and has higher cost performance and higher competitiveness in market popularization. The method comprises the following steps of S1 determining the specification of a chip SiP memory die, S2 collecting position information of each welding point graph of signals on the memory die, S3 adjusting the position of a main control die memory PHY interface welding point according to the information collected in S2 when the rear end of the main control die is designed, enabling the position of the main control die DDR memory PHY interface welding point to be consistent with the sequence of interface welding points of the memory die, S4 placing the main control die and the memory die on the same level on a substrate, and realizing one-to-one mapping and routing of the main control die memory PHY to the memory die through bonding wires.

Inventors

• DING HAISONG

Assignees

• 合肥君正科技有限公司

Dates

Publication Date

20260512

Application Date

20201027

Claims (4)

1. 1. The SiP packaging design method of the IPC monitoring chip is characterized by comprising the following steps of: S1, determining the specification of a chip SiP memory die (4); S2, collecting position information of each welding spot image of signals on a memory die (4), wherein the positions of each welding spot image of the signals on the memory die are positions of welding spots (7) of an interface, including welding spots A0, A1, A2, A3, A4, A5 and A6; S3, adjusting the positions of main die memory PHY interface welding spots (8) according to the information collected in the S2 when the rear end of the main die (1) is designed, so that the sequences of the main die memory PHY interface welding spots (8) and the interface welding spots (7) of the memory die are kept consistent, wherein the main die memory PHY interface welding spots (8) comprise the positions of a0, a1, a2, a3, a4, a5 and a6 welding spots; S4, placing the main control die (1) and the memory die (4) on the same level on the substrate, and realizing one-to-one mapping and routing of the main control die memory PHY to the memory die through the bonding wire (3), namely, utilizing the layout of die in the package and adjusting the signal distribution sequence of the main control die memory PHY interface to enable signal welding spots of the main control die and the memory die to be in one-to-one mapping, so that the main control die and the memory die are directly and wiredly connected through the bonding wire, and thus an RDL layer is omitted.
2. 2. The SiP package design method of an IPC monitor chip according to claim 1, wherein the main control die (1) and the other signals of the memory die (4) in S3 are processed similarly through bonding wire interconnection pads.
3. 3. The method of claim 1, wherein in S4, the substrate is replaced by a frame, and the substrate or the frame is a carrier for each wafer die in the SiP package.
4. 4. The SiP packaging design method of the IPC monitoring chip according to claim 1 is characterized in that a packaging substrate is a carrier for packaging wafer die inside the method, other signals related to a main control die and a memory die are wired on the packaging substrate through bonding wires and then connected to solder balls to form the visible chip packaging, the main control die is a main signal processing unit of the IPC chip, the memory die is a DDR memory unit operated by an IPC system, the memory PHY interface welding spots are located at the edge of the main control die, information interaction is carried out between the main control die and the memory die through design layout of the rear end of the main control die, and the bonding wires are interconnection wires of the main control die memory PHY interface welding spots and the memory die interface welding spots.

Description

SiP packaging design method of IPC monitoring chip Technical Field The invention relates to the technical field of semiconductor packaging, in particular to a SiP packaging design method of an IPC monitoring chip. Background Integrated circuits can be classified into application-specific integrated circuits and general-purpose integrated circuits, i.e., application-specific chips and general-purpose chips, in terms of application. The special chip has the characteristics of high reliability, good performance, high function utilization rate and the like, and the universal chip has the characteristics of strong universality, high portability, good expansibility and the like. With the development of electronic engineering, from the initial development of a single component, a stage of aggregating multiple components to develop into a system is gradually advanced. Under the requirements of high efficiency and light and thin appearance of the product, chips with different functions start to move to the integration stage. During this time, the continuous development and breakthrough of packaging technology has become one of the forces driving integration, and SiP concepts have been proposed. SiP as a packaging technology refers to a method of concentrating multiple die into a single package, thereby enabling the die to obtain system functions. The internal electronic devices of the IPC monitoring products in the market at present mainly comprise a main control chip, a system operation memory chip, a storage chip for storing operation programs, a network transmission chip, an image sensor chip and the like. The main control chip and the memory chip are complex in interconnection lines on the PCB, the memory chip occupies a relatively large PCB area, in order to simply and conveniently design PCB hardware of the IPC monitoring product and reduce development cost, the IPC monitoring chip generally adopts the SiP technology to integrate and seal the main control chip die and the memory DDR chip die into one chip, the side view of the common SiP stacking mode of the IPC monitoring chip is shown in the figure 1 at present, the main control die 1 is arranged on the top, and the memory DDR die 4 is arranged on the bottom. However, the pressure welding point of the existing general memory DDR die 4 is located at a die middle position, which requires RDL 2 (as shown in an example of fig. 2) to arrange the pressure welding point to a die edge position, so that the DDR PHY interface of the main control die and the memory die bonding wire 4 are conveniently interconnected. At present, the market competition of the IPC monitoring chip is vigorous, how to reduce the cost of the IPC monitoring chip and realize the basically unchanged function becomes a requirement of wide attention increasingly. Common technical terms in the prior art include: The SIP package (SYSTEM IN A PACKAGE system-in-package) is a packaging scheme that integrates multiple functional wafers, including a processor, a memory, and other functional wafers, into one package according to the application scenario, the number of package substrate layers, and other factors, so as to realize a substantially complete function. Die, wafer die, is a small unit in a silicon wafer that includes a single chip designed to be complete and a portion of the scribe line area of the chip adjacent to the horizontal and vertical directions. Grains are small crystals of irregular shape that constitute a polycrystalline body, and each grain sometimes consists of a plurality of subgrains that differ slightly in bit direction. The average diameter of the grains is typically in the range of 0.015 to 0.25mm, while the average diameter of the subgrain is typically on the order of 0.001 mm. The abbreviation for RDL Redistribution Layer rerouting layer is that the bond pads can be rearranged to any reasonable location on wafer die. Conventional center pads through die can be reassigned to die perimeter using RDL technology. IPC-abbreviation for IP Camera, IP is Internet protocol, camera is Camera, video Camera, IP Camera is web Camera as the name implies, it is a new generation of video Camera produced by combining traditional video Camera with web technology. The abbreviation of Printed Circuit Board printed circuit board is an important electronic component, is a support for electronic components, and is a carrier for electrical connection of electronic components. It is called a "printed" circuit board because it is made using electronic printing. The memory PHY is a memory physical layer, and common network card chips integrate MAC and PHY into one chip, but at present, south bridge chips of a plurality of mainboards already comprise Ethernet MAC control functions, and only do not provide a physical layer interface, so that the PHY chips are required to be externally connected to provide an access channel of Ethernet. The PHY network chip is commonly called as a soft network card chip,