CN-114496918-B - Integrated circuit structure and forming method thereof

Abstract

A method of forming an integrated circuit structure includes forming source/drain regions of a transistor, forming a first interlayer dielectric over the source/drain regions, and forming lower source/drain contact plugs over the source/drain regions, with the lower source/drain contact plugs electrically coupled to the source/drain regions. The lower source/drain contact plug extends into the first interlayer dielectric. The method further includes depositing an etch stop layer over the first interlayer dielectric and the lower source/drain contact plugs, depositing a second interlayer dielectric over the etch stop layer, and performing an etch process to etch the second interlayer dielectric, the etch stop layer, and an upper portion of the first interlayer dielectric to form openings, with top surfaces and sidewalls of the lower source/drain contact plugs exposed to the openings, and forming upper contact plugs in the openings. Embodiments of the invention also relate to an integrated circuit structure and another integrated circuit structure.

Inventors

• LAI YINGYU
• LIN ZHIXUAN
• CHEN XIZHONG
• LIAO ZHITENG

Assignees

• 台湾积体电路制造股份有限公司

Dates

Publication Date

20260512

Application Date

20220121

Priority Date

20210527

Claims (20)

1. 1. A method of forming an integrated circuit structure, comprising: Forming source/drain regions of the transistor; forming a first interlayer dielectric over the source/drain regions; Forming a lower source/drain contact plug over the source/drain region and electrically coupled to the source/drain region, wherein the lower source/drain contact plug extends into the first interlayer dielectric, and wherein the lower source/drain contact plug comprises: diffusion barrier, and A metallic material on the diffusion barrier; depositing an etch stop layer over the first interlayer dielectric and the lower source/drain contact plugs; Depositing a second interlayer dielectric over the etch stop layer; Performing an etching process to etch an upper portion of the second interlayer dielectric, the etch stop layer, and the first interlayer dielectric to form an opening, and a top surface and sidewalls of the lower source/drain contact plug are exposed to the opening, wherein during the etching process, portions of the diffusion barrier are etched to expose vertical sidewalls of the metal material, and An upper contact plug is formed in the opening, the upper contact plug contacting the vertical sidewall of the metal material.
2. 2. The method of claim 1, wherein the vertical sidewall is laterally offset from an inner sidewall of the diffusion barrier.
3. 3. The method of claim 2, wherein the etch stop layer and the upper portion of the first interlayer dielectric are etched using a process gas comprising a fluorine and carbon containing gas.
4. 4. The method of claim 3, wherein the diffusion barrier is also etched using the process gas comprising the fluorine and carbon containing gas and H 2 O.
5. 5. The method of claim 1, further comprising: after forming the upper contact plug, an implantation process is performed to implant the second interlayer dielectric.
6. 6. The method of claim 5, wherein the implantation process is performed using a dopant comprising Ge, xe, ar, si or a combination thereof.
7. 7. The method of claim 1, wherein the first interlayer dielectric has a thickness and the opening extends into the first interlayer dielectric to a depth, and wherein a ratio of the depth to the thickness is in a range between 0.1 and 0.5.
8. 8. The method of claim 1, wherein the upper portions of the second and first interlayer dielectrics are etched using a same etch mask.
9. 9. The method of claim 1, further comprising: Forming a gate stack, wherein the gate stack and the source/drain regions are adjacent to each other, and Forming a gate contact plug, wherein the gate contact plug is aligned with a vertical middle line of the gate stack.
10. 10. An integrated circuit structure, comprising: A gate stack over the semiconductor region; source/drain regions on one side of the gate stack; Source/drain silicide regions over the source/drain regions; a first interlayer dielectric over the source/drain silicide regions; A lower source/drain contact plug located over and contacting the source/drain silicide region, wherein the lower source/drain contact plug comprises: a diffusion barrier comprising a first portion and a second portion, wherein a first tip of the first portion is lower than a second tip of the second portion, and A metallic material between the first and second portions of the diffusion barrier; An etch stop layer over the first interlayer dielectric and the lower source/drain contact plugs; a second interlayer dielectric over the etch stop layer, and An upper source/drain contact plug penetrating the second interlayer dielectric and the etch stop layer and extending into an upper portion of the first interlayer dielectric, wherein a first sidewall of the upper source/drain contact plug contacts a second sidewall of the metal material and a bottom surface of the upper source/drain contact plug contacts a first top end of the diffusion barrier layer.
11. 11. The integrated circuit structure of claim 10, wherein the etch stop layer comprises a dielectric material of SiN, siCN, siC, alO, alN, siOCN or a composite layer thereof.
12. 12. The integrated circuit structure of claim 10, wherein the diffusion barrier comprises titanium nitride and the metallic material comprises a material selected from tungsten, cobalt, and combinations thereof.
13. 13. The integrated circuit structure of claim 10, further comprising a gate contact plug located over and contacting the gate stack, wherein the gate contact plug and a middle line of the gate stack are vertically aligned.
14. 14. The integrated circuit structure of claim 10, wherein a third sidewall of the upper source/drain contact plug contacts a fourth sidewall of the lower source/drain contact plug, and wherein the second sidewall and the fourth sidewall are opposing sidewalls of the lower source/drain contact plug.
15. 15. The integrated circuit structure of claim 10, wherein the first interlayer dielectric has a thickness and the upper source/drain contact plug extends into the first interlayer dielectric to a depth, and wherein a ratio of the depth to the thickness is in a range between 0.1 and 0.5.
16. 16. The integrated circuit structure of claim 10, further comprising germanium in an upper half of the second interlayer dielectric.
17. 17. An integrated circuit structure, comprising: a semiconductor region; Source/drain regions extending into the semiconductor region; A first interlayer dielectric over the source/drain regions; A first source/drain contact plug located over and electrically coupled to the source/drain region, wherein the first source/drain contact plug comprises: A metal region; a metal nitride layer having a first portion surrounding the metal region, and A metal layer having a second portion surrounding the metal nitride layer, and The second source/drain contact plug includes: A first sidewall in physical contact with a second sidewall of the metal region to form a vertical interface, and A bottom edge in physical contact with top edges of the metal nitride layer and the metal layer, the bottom edge comprising a first bottom surface and a second bottom surface, the first bottom surface contacting a first top surface of the first source/drain contact plug, and the second bottom surface contacting a second top surface of the first source/drain contact plug, wherein the second bottom surface is lower than the first bottom surface, and wherein the first sidewall connects the first bottom surface and the second bottom surface.
18. 18. The integrated circuit structure of claim 17, wherein the metal region comprises a material selected from tungsten, cobalt, and combinations thereof.
19. 19. The integrated circuit structure of claim 17, wherein the second source/drain contact plug extends into the first interlayer dielectric to a depth, and a ratio of the depth to a thickness of the first interlayer dielectric is in a range between 0.1 and 0.5.
20. 20. The integrated circuit structure of claim 17, further comprising: an etch stop layer over the first interlayer dielectric, and A second interlayer dielectric over the etch stop layer, wherein the second source/drain contact plug also extends into the etch stop layer and the second interlayer dielectric.

Description

Integrated circuit structure and forming method thereof Technical Field Embodiments of the invention relate to integrated circuit structures and methods of manufacturing the same. Background In the fabrication of integrated circuits, contact plugs are used to electrically couple to the source and drain regions and the gate of a transistor. Source/drain contact plugs are typically connected to the source/drain silicide regions, and the formation process includes forming contact openings to expose the source/drain regions, depositing a metal layer, depositing a barrier layer over the metal layer, performing an annealing process to react the metal layer with the source/drain regions, filling metal into the remaining contact openings, and performing a Chemical Mechanical Polishing (CMP) process to remove the excess metal. Disclosure of Invention Some embodiments of the present invention provide a method of forming an integrated circuit structure, comprising forming a source/drain region of a transistor, forming a first interlayer dielectric over the source/drain region, forming a lower source/drain contact plug over the source/drain region and electrically coupled to the source/drain region, wherein the lower source/drain contact plug extends into the first interlayer dielectric, depositing an etch stop layer over the first interlayer dielectric and the lower source/drain contact plug, depositing a second interlayer dielectric over the etch stop layer, performing an etch process to etch an upper portion of the second interlayer dielectric, the etch stop layer, and the first interlayer dielectric, and forming an opening with a top surface and a sidewall of the lower source/drain contact plug exposed to the opening, and forming an upper contact plug in the opening. Further embodiments of the present invention provide an integrated circuit structure comprising a gate stack over a semiconductor region, a source/drain region on one side of the gate stack, a source/drain silicide region over the source/drain region, a first interlayer dielectric over the source/drain silicide region, a lower source/drain contact plug over and contacting the source/drain silicide region, an etch stop layer over the first interlayer dielectric and the lower source/drain contact plug, a second interlayer dielectric over the etch stop layer, and an upper source/drain contact plug extending through the second interlayer dielectric and the etch stop layer and into an upper portion of the first interlayer dielectric, wherein a first sidewall of the upper source/drain contact plug contacts a second sidewall of the lower source/drain contact plug. Still further embodiments of the present invention provide an integrated circuit structure comprising a semiconductor region, a source/drain region extending into the semiconductor region, a first interlayer dielectric over the source/drain region, a first source/drain contact plug over the source/drain region and electrically coupled to the source/drain region, wherein the first source/drain contact plug comprises a metal region, a metal nitride layer having a first portion surrounding the metal region, and a metal layer having a second portion surrounding the metal nitride layer, and the second source/drain contact plug comprises a first sidewall in physical contact with the second sidewall of the metal region to form a vertical interface, and a bottom edge in physical contact with the metal nitride layer and a top edge of the metal layer. Drawings Aspects of the invention are best understood from the following detailed description when read in connection with the accompanying drawing figures. It is noted that the various components are not drawn to scale according to standard practice in the industry. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. Fig. 1-7, 8A, 8B, 9A, 9B, 10A, 10B, and 11-20 are perspective and cross-sectional views of intermediate stages of forming a transistor and corresponding contact plug according to some embodiments. Fig. 21 illustrates a process flow for forming a transistor and a contact plug in accordance with some embodiments. Detailed Description The following disclosure provides many different embodiments, or examples, of the different components used to implement the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component over or on a second component may include embodiments in which the first component and the second component are formed in direct contact, and may also include examples in which additional components may be formed between the first component and the second component, such that the first component and the second component may not be in direct contact. Furthermore, the present inventio