CN-114499430-B - Structure and method for controlling electrostatic discharge (ESD) events in a resistor-capacitor circuit

Abstract

Embodiments of the present disclosure provide a circuit structure and method of controlling electrostatic discharge (ESD) events in a resistor-capacitor (RC) circuit. A circuit structure according to the present disclosure may include a trigger transistor coupled in parallel with an RC circuit, and a gate terminal coupled to a portion of the RC circuit. A mirror transistor coupled in parallel with the RC circuit delivers a current that is less than the current through the trigger transistor. The snapback device has a gate terminal coupled to the source or drain of the mirror transistor, and an anode/cathode terminal pair coupled in parallel with the RC circuit. The current at the gate terminal of the snapback device, derived from the current in the mirror transistor, controls the anode/cathode current flow in the snapback device.

Inventors

• A - F - Loiseau
• GAUTHIER JR ROBERT J
• S. MITRA
• LI YOU
• M.Miao
• LIANG WEI

Assignees

• 格芯(美国)集成电路科技有限公司

Dates

Publication Date

20260512

Application Date

20211027

Priority Date

20201028

Claims (20)

1. 1. A circuit structure, comprising: A resistor-capacitor RC circuit having a first node, a second node separated from the first node by a resistive element and a capacitive element, and a third node between the resistive element and the capacitive element; a trigger transistor having a source/drain S/D terminal pair coupled between the first node and the second node and in parallel with the RC circuit, and a gate terminal coupled to the third node of the RC circuit; A mirror transistor having a pair of S/D terminals coupled between the first node and the second node and in parallel with the RC circuit, and a gate terminal coupled to the gate terminal of the trigger transistor, wherein the pair of S/D terminals of the mirror transistor is configured to transmit a current less than a current through the pair of S/D terminals of the trigger transistor, and A snapback device having a gate terminal coupled to a selected one of the S/D terminal pairs of the mirror transistor, and an anode/cathode terminal pair coupled between the first node and the second node and in parallel with the RC circuit, wherein a current at the gate terminal controls an anode/cathode current flow in the snapback device.
2. 2. The circuit structure of claim 1, further comprising: A first inverter having an input coupled to the third node of the RC circuit and an output coupled to the gate terminal of the trigger transistor, and A second inverter having an input coupled to a selected one of the S/D terminals of the mirror transistor and an output coupled to the gate terminal of the snapback device, Wherein the trigger transistor and the mirror transistor are configured to invert a voltage polarity between the output of the first inverter and the input of the second inverter.
3. 3. The circuit structure of claim 1, wherein a current through the S/D terminal pair of the mirror transistor is at most 1/10 of a current through the S/D terminal pair of the trigger transistor.
4. 4. The circuit structure of claim 1, wherein a current through the S/D terminal pair of the mirror transistor is at most twenty milliamp mA and a current through the S/D terminal pair of the trigger transistor is at most two hundred mA.
5. 5. The circuit structure of claim 1, wherein a source-to-drain width of the trigger transistor is at most four thousand micrometers μιη and a source-to-drain width of the mirror transistor is at most two hundred μιη.
6. 6. The circuit structure of claim 1, further comprising a resistor coupled between a selected one of the S/D terminal pairs of the mirror transistor and the first node, wherein the resistor is configured to transmit current through the mirror transistor.
7. 7. The circuit structure of claim 1, wherein the snapback device comprises a silicon controlled rectifier SCR.
8. 8. A circuit structure, comprising: A resistor-capacitor RC circuit having a first node, a second node separated from the first node by a resistive element and a capacitive element, and a third node between the resistive element and the capacitive element; a trigger transistor having a source/drain S/D terminal pair coupled between the first node and the second node and in parallel with the RC circuit, and a gate terminal coupled to the third node of the RC circuit; a mirror transistor having a pair of S/D terminals coupled between the first node and the second node and in parallel with the RC circuit, and a gate terminal coupled to the gate terminal of the trigger transistor, wherein a current through the pair of S/D terminals of the mirror transistor is less than a current through the pair of S/D terminals of the trigger transistor, and A snapback device having a gate terminal for controlling current flow in the snapback device, the snapback device comprising: a P-well having a first N-doped region coupled to one of the first nodes; An N-well adjacent to the P-well and having a first P-doped region coupled to the second node, wherein a current path from the first node to the second node through the snapback device is in parallel with the RC circuit, and At least one doped region within the P-well or the N-well coupled to a selected one of the pair of S/D terminals of the mirror transistor and defining the gate terminal of the snapback device, wherein the at least one doped region has the same doping type relative to the P-well or the N-well.
9. 9. The circuit structure of claim 8, further comprising: A first inverter having an input coupled to the third node of the RC circuit and an output coupled to the gate terminal of the trigger transistor, and A second inverter having an input coupled to a selected one of the S/D terminals of the mirror transistor and an output coupled to the gate terminal of the snapback device, Wherein the trigger transistor and the mirror transistor are configured to invert a voltage polarity between the output of the first inverter and the input of the second inverter.
10. 10. The circuit structure of claim 8, wherein a current through the S/D terminal pair of the mirror transistor is at most 1/10 of a current through the S/D terminal pair of the trigger transistor.
11. 11. The circuit structure of claim 8, wherein a current through the S/D terminal pair of the mirror transistor is at most twenty milliamp mA and a current through the S/D terminal pair of the trigger transistor is at most two hundred mA.
12. 12. The circuit structure of claim 8, wherein a source-to-drain width of the trigger transistor is at most four thousand micrometers μιη and a source-to-drain width of the mirror transistor is at most two hundred μιη.
13. 13. The circuit structure of claim 8, further comprising a resistor coupled between a selected one of the pair of S/D terminals of the mirror transistor and the first node, wherein the resistor is configured to transmit current through the mirror transistor.
14. 14. The circuit structure of claim 8, wherein the snapback device comprises a silicon controlled rectifier SCR.
15. 15. The circuit structure of claim 14, wherein at least one doped region within the P-well or the N-well comprises a second P-doped region within the P-well and a second N-doped region within the N-well.
16. 16. A method for controlling an electrostatic discharge, ESD, event in a resistor-capacitor, RC, circuit, the method comprising: Transmitting an electrostatic discharge, ESD, current through a trigger transistor in parallel with a resistor-capacitor, RC, circuit, the RC circuit comprising a first node, a second node separated from the first node by a resistive element and a capacitive element, and a third node coupled to a gate of the trigger transistor between the resistive element and the capacitive element; transmitting a mirrored current through a mirrored transistor in parallel with the trigger transistor, wherein the mirrored transistor is configured to transmit a current less than the transmitted ESD current, and The mirrored current is transferred to a gate terminal of a snapback device electrically coupled between the first node and the second node and in parallel with the RC circuit to cause current to flow from the first node to the second node through the snapback device during transfer of the mirrored current to the gate terminal.
17. 17. The method of claim 16, wherein transmitting the mirrored current comprises preventing the mirrored current from exceeding at most 1/10 th of the transmitted ESD current.
18. 18. The method of claim 16, wherein transmitting the ESD current comprises preventing the ESD current from exceeding 200 milliamp mA and transmitting the mirrored current comprises preventing the mirrored current from exceeding 20 milliamp mA.
19. 19. The method of claim 16, further comprising applying a reverse node voltage within the RC circuit to a gate terminal of the trigger transistor to pass the ESD current through the trigger transistor, and wherein passing the mirrored current to the gate terminal of the snapback device comprises applying a reverse voltage of a source/drain voltage of the mirrored transistor to the gate terminal of the snapback device.
20. 20. The method of claim 16, wherein the snapback device comprises a silicon controlled rectifier SCR.

Description

Structure and method for controlling electrostatic discharge (ESD) events in a resistor-capacitor circuit Technical Field Embodiments of the present disclosure generally relate to electronic circuits. More specifically, various embodiments of the present disclosure provide circuit structures and methods for controlling electrostatic discharge (ESD) events in a resistor-capacitor circuit. Background Circuits including Integrated Circuits (ICs) may include components for protecting device hardware from electrostatic discharge (ESD) voltages that may cause electrical shorts, dielectric breakdown, and/or other failure modes. In an ideal arrangement, the ESD element has no effect on device operation until a pin on the IC sees an ESD event, where the ESD event acts as a trigger voltage that turns on the ESD device and discharges current through the ESD element to either the power rail or the ground rail. The ESD element is not used for any operational purpose until a trigger voltage is applied to the ESD element to activate it. With the increasing demands for low leakage and longer battery life, typical power clamps using large FETs as discharge elements often suffer from excessive leakage. Other problems often occur when replacing large FETs with "snapback devices" to solve the leakage problem. Snapback device refers to a specific kind of device in which once enabled, the current remains on even after a signal is applied to the gate terminal of the snapback device (i.e., "latch"). Conventional arrangements of ESD elements and/or other structures cannot provide a stable trigger voltage while preventing latch-up to ensure that the ESD element is active only during an ESD event. Disclosure of Invention Some aspects of the present disclosure provide a circuit structure comprising a resistor-capacitor (RC) circuit having a first node, a second node separated from the first node by a resistive element and a capacitive element, and a third node between the resistive element and the capacitive element, a trigger transistor having a source/drain (S/D) terminal pair coupled between the first node and the second node and in parallel with the RC circuit, and a gate terminal coupled to the third node of the RC circuit, a mirror transistor having an S/D terminal pair coupled between the first node and the second node and in parallel with the RC circuit, and a gate terminal coupled to the gate terminal of the trigger transistor, wherein the S/D terminal pair of the mirror transistor is configured to transmit a current less than a current through the S/D terminal pair of the trigger transistor, and a snapback device having a mirror current coupled to the one of the RC terminals and to the gate terminal of the trigger transistor and a control device in parallel with the gate terminal of the RC circuit. Still other aspects of the present disclosure provide a circuit structure including a resistance-capacitance (RC) circuit having a first node, a second node separated from the first node by a resistive element and a capacitive element, and a third node between the resistive element and the capacitive element; a trigger transistor having a pair of source/drain (S/D) terminals coupled between the first node and the second node and in parallel with the RC circuit, and a gate terminal coupled to the third node of the RC circuit, a mirror transistor having a pair of S/D terminals coupled between the first node and the second node and in parallel with the RC circuit, and a gate terminal coupled to the gate terminal of the trigger transistor, wherein a current through the pair of S/D terminals of the mirror transistor is less than a current through the pair of S/D terminals of the trigger transistor, and a snapback device having a gate terminal for controlling a current flow in the snapback device, the snapback device comprising a P-well having a first N-doped region coupled to the first node, an N-well adjacent to the P-well and having a first P-doped region coupled to the second node, wherein a current through the snapback device from the first node and a mirror transistor is coupled to at least one of the gate terminals of the pair of the first node and the snapback device defining a P-well, wherein the at least one doped region has the same doping type relative to the P-well or the N-well. Still further aspects of the present disclosure provide a method for controlling an electrostatic discharge (ESD) event in a resistor-capacitor (RC) circuit, the method comprising transmitting an electrostatic discharge (ESD) current through a trigger transistor in parallel with the RC circuit, the RC circuit comprising a first node, a second node separated from the first node by a resistive element and a capacitive element, and a third node coupled to a gate of the trigger transistor between the resistive element and the capacitive element, transmitting a mirror current through a mirror transistor in parallel with the trigger transistor, wherein t