CN-114512156-B - Module board, storage module and storage system

Abstract

A module board, a memory module, and a memory system are provided. The module board includes a first branch line for connecting a clock signal terminal provided on at least one surface to a first branch point, a first signal line for connecting the first branch point to the first module clock signal terminal, a second signal line for connecting the first module clock signal terminal to the kth module clock signal terminal with a first termination resistor terminal, a third signal line for connecting the first branch point to the kth+1 module clock signal terminal, and a fourth signal line for connecting the kth+1 module clock signal terminal to the 2 kth module clock signal terminal and a second termination resistor terminal, wherein a length of the third signal line is greater than a sum of a length of the first signal line and a length of the second signal line.

Inventors

• Li Yuanxie
• Pu Huanxu
• BAI ZHENGXUN
• JIN DUHENG
• WEN SHENGXI
• XU DONGYUN
• AN ZHENWU

Assignees

• 三星电子株式会社

Dates

Publication Date

20260512

Application Date

20210803

Priority Date

20201116

Claims (20)

1. 1. A modular plate, the modular plate comprising: a plurality of stacked layers including first to nth layers; First to kth module clock signal terminals arranged in a component area of at least one of an upper surface of the first layer and a lower surface of the nth layer at a first predetermined interval; k+1th to 2k-th module clock signal terminals, the k+1th to 2k-th module clock signal terminals being arranged in the component area at a second predetermined interval; A first termination resistor terminal disposed adjacent to the kth module clock signal terminal; a second termination resistor terminal disposed adjacent to the 2k module clock signal terminal; A plurality of terminals arranged in a terminal area of the at least one surface and including clock signal terminals; A first branch line for connecting the clock signal terminal provided on the at least one surface to a first branch point; A first signal line for connecting the first branch point to the first module clock signal terminal; The second signal line is used for sequentially connecting the first module clock signal terminal to the kth module clock signal terminal with the first connecting resistor terminal; A third signal line for connecting the first branch point to the k+1th module clock signal terminal, and A fourth signal line for sequentially connecting the k+1th module clock signal terminal to the 2k module clock signal terminal with the second terminating resistor terminal, The length of the third signal line is greater than the sum of the length of the first signal line and the length of the second signal line.
2. 2. The module board of claim 1, wherein the first predetermined interval is equal to the second predetermined interval, the length of the second signal line is equal to the length of the fourth signal line, and the length of the second signal line is greater than the length of the first signal line.
3. 3. The module board according to claim 2, wherein the first signal line, the second signal line, the third signal line, and the fourth signal line are provided on at least one surface of the first layer to the n-th layer other than the at least one surface.
4. 4. The modular plate of claim 2, wherein the modular plate further comprises: first through kth module command/address terminals, the first to kth module command/address terminals are arranged in the component area at the first predetermined interval; A k+1th module command/address terminal to a 2k module command/address terminal, the k+1th module command/address terminal to the 2k module command/address terminal being arranged in the component area at the second predetermined interval, and A third end resistor terminal disposed adjacent to the 2k module command/address terminal, Wherein the plurality of terminals further comprises command/address terminals.
5. 5. The modular plate of claim 4, wherein the modular plate further comprises: A second branch line for connecting the command/address terminal provided on the at least one surface to a second branch point; a fifth signal line for connecting the second branch point to the first module command/address terminal, and A sixth signal line for sequentially connecting the first to the 2 k-th module command/address terminals with the third connecting resistance terminal, Wherein the sum of the length of the second branch line and the length of the fifth signal line is equal to the sum of the length of the first branch line and the length of the first signal line.
6. 6. The module board according to claim 5, wherein the fifth signal line and the sixth signal line are provided on at least one surface of the first layer to the n-th layer other than the at least one surface.
7. 7. The modular plate of claim 4, wherein the modular plate further comprises: a fourth terminal resistor terminal disposed adjacent to the kth module command/address terminal; A second branch line for connecting the command/address terminal provided on the at least one surface to a second branch point; A fifth signal line for connecting the second branch point to the first module command/address terminal; A sixth signal line for sequentially connecting the first to the kth module command/address terminals with the fourth terminal resistor terminal; a seventh signal line for connecting the second branch point to the k+1-th module command/address terminal, and An eighth signal line for sequentially connecting the k+1th module command/address terminal to the 2k module command/address terminal with the third terminal resistor terminal, Wherein the length of the seventh signal line is greater than the sum of the length of the fifth signal line and the length of the sixth signal line.
8. 8. The module board of claim 7, wherein the length of the sixth signal line is equal to the length of the eighth signal line, The length of the sixth signal line is longer than that of the fifth signal line, and The sum of the length of the second branch line and the length of the fifth signal line is equal to the sum of the length of the first branch line and the length of the first signal line.
9. 9. The module board according to claim 8, wherein the fifth signal line, the sixth signal line, the seventh signal line, and the eighth signal line are provided on at least one surface of the first layer to the n-th layer other than the at least one surface.
10. 10. The modular plate of claim 4, wherein the modular plate comprises: A fourth terminal resistor terminal disposed adjacent to the 2k-1 module command/address terminal; A second branch line for connecting the command/address terminal provided on the at least one surface to a second branch point; A fifth signal line for connecting the second branch point to the first module command/address terminal; A sixth signal line for sequentially connecting odd-numbered ones of the first to 2k-1 th module command/address terminals with the fourth terminal resistor terminal; A seventh signal line for connecting the second branch point to a second module command/address terminal of the first to 2k-1 th module command/address terminals, and An eighth signal line for sequentially connecting even-numbered ones of the second to the 2 k-th module command/address terminals with the third connecting resistance terminal, Wherein the length of the fifth signal line is equal to the length of the seventh signal line, and the sum of the length of the second branch line and the length of the fifth signal line is equal to the sum of the length of the first branch line and the length of the first signal line.
11. 11. The module board according to claim 10, wherein the fifth signal line, the sixth signal line, the seventh signal line, and the eighth signal line are provided on at least one surface of the first layer to the n-th layer other than the at least one surface.
12. 12. A memory module, the memory module comprising: A modular plate, the modular plate comprising: a plurality of stacked layers including first to nth layers; First to kth module clock signal terminals arranged in a component area of at least one of an upper surface of the first layer and a lower surface of the nth layer at a first predetermined interval; k+1th to 2k-th module clock signal terminals, the k+1th to 2k-th module clock signal terminals being arranged in the component area at a second predetermined interval; A first termination resistor terminal disposed adjacent to the kth module clock signal terminal; A first termination resistor connected to the first termination resistor terminal; a second termination resistor terminal disposed adjacent to the 2k module clock signal terminal; A second termination resistor connected to the second termination resistor terminal; A plurality of terminals arranged in a terminal area of the at least one surface and including clock signal terminals; A first branch line for connecting the clock signal terminal provided on the at least one surface to a first branch point; A first signal line for connecting the first branch point to the first module clock signal terminal; The second signal line is used for sequentially connecting the first module clock signal terminal to the kth module clock signal terminal with the first connecting resistor terminal; a third signal line for connecting the first branch point to the k+1-th module clock signal terminal; a fourth signal line for sequentially connecting the k+1th module clock signal terminal to the 2k module clock signal terminal with the second termination resistor terminal; First through kth semiconductor memory devices, the first to kth semiconductor memory devices respectively include first to kth memory clock signal terminals respectively mounted at the first to kth module clock signal terminals; and The k+1th semiconductor memory device to the 2k semiconductor memory device, the k+1th to 2k semiconductor memory devices respectively include k+1th to 2k memory clock signal terminals respectively installed at the k+1th to 2k < th > module clock signal terminals, The length of the third signal line is greater than the sum of the length of the first signal line and the length of the second signal line.
13. 13. The memory module of claim 12, wherein the first predetermined interval is equal to the second predetermined interval, the length of the second signal line is equal to the length of the fourth signal line, and the length of the second signal line is greater than the length of the first signal line.
14. 14. The memory module of claim 13, wherein: Each of the first through 2 k-th semiconductor memory devices is a dual-core packaged semiconductor memory device including a stacked first die and second die; Each of the first die and the second die is a double data rate semiconductor memory device, and The memory module is a bufferless dual inline memory module or a small dual inline memory module.
15. 15. The memory module according to claim 13, wherein the first signal line, the second signal line, the third signal line, and the fourth signal line are provided on at least one surface of the first layer to the n-th layer other than the at least one surface.
16. 16. The memory module of claim 13, wherein the module board further comprises: first through kth module command/address terminals, the first to kth module command/address terminals are arranged in the component area at the first predetermined interval; A k+1th module command/address terminal to a 2k module command/address terminal, the k+1th module command/address terminal to the 2k module command/address terminal being arranged in the component area at the second predetermined interval, and A third end resistor terminal disposed adjacent to the 2k module command/address terminal, Wherein: First to kth memory command/address terminals are also respectively mounted at the first to kth module command/address terminals, and The k+1th to 2k-th memory clock signal terminals are also mounted at the k+1th to 2k-th module command/address terminals, respectively.
17. 17. The memory module of claim 16, the memory module further comprising: A second branch line for connecting the command/address terminal provided on the at least one surface to a second branch point; a fifth signal line for connecting the second branch point to the first module command/address terminal, and A sixth signal line for sequentially connecting the first to the 2 k-th module command/address terminals with the third connecting resistance terminal, Wherein the sum of the length of the second branch line and the length of the fifth signal line is equal to the sum of the length of the first branch line and the length of the first signal line.
18. 18. The memory module according to claim 17, wherein the fifth signal line and the sixth signal line are provided on at least one surface of the first layer to the n-th layer other than the at least one surface.
19. 19. The memory module of claim 16, the memory module further comprising: a fourth terminal resistor terminal disposed adjacent to the kth module command/address terminal; A second branch line for connecting the command/address terminal provided on the at least one surface to a second branch point; A fifth signal line for connecting the second branch point to the first module command/address terminal; A sixth signal line for sequentially connecting the first to the kth module command/address terminals with the fourth terminal resistor terminal; a seventh signal line for connecting the second branch point to the k+1-th module command/address terminal, and An eighth signal line for sequentially connecting the k+1th module command/address terminal to the 2k module command/address terminal with the third terminal resistor terminal, Wherein the length of the seventh signal line is greater than the sum of the length of the fifth signal line and the length of the sixth signal line.
20. 20. The memory module of claim 19, wherein the length of the sixth signal line is equal to the length of the eighth signal line, The length of the sixth signal line is longer than that of the fifth signal line, and The sum of the length of the second branch line and the length of the fifth signal line is equal to the sum of the length of the first branch line and the length of the first signal line.

Description

Module board, storage module and storage system Cross Reference to Related Applications The present application claims priority from korean patent application No.10-2020-0152459 filed in the korean intellectual property office on 11/16 th 2020, the disclosure of which is incorporated herein by reference in its entirety. Technical Field One or more embodiments of the present disclosure relate to a module board, a memory module, and a memory system. Background The memory module may include a plurality of semiconductor memory devices mounted on a module board. Depending on whether the memory module further includes a buffer on the module board, the memory module may be divided into a server-oriented memory module and a PC-oriented (client-oriented) memory module. The server-oriented storage module includes a buffer, so signals of various levels applied from external devices (e.g., a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), etc.) may be converted (e.g., amplified) and the converted signals may be transferred to a plurality of storage devices. Therefore, in the server-oriented memory module, even if the loads of the plurality of semiconductor memory devices are large, the quality of the clock signal and/or the command/address is not affected. On the other hand, the PC-oriented memory module does not include a buffer on the module board, and thus a signal applied from an external device can be transmitted to a plurality of semiconductor memory devices without converting signals of various levels. Therefore, in a PC-oriented memory module, when the load number of the semiconductor memory device is large, the quality of the clock signal and/or the command/address may be degraded. Disclosure of Invention Summary of the inventionone or more embodiments of the present disclosure provide a module board in which the quality of clock signals and/or command/addresses is not affected even if the loads of a plurality of semiconductor memory devices are large, and a memory module including the module board. The technical problems solved by one or more embodiments are not limited to the above technical problems, and other technical problems not described herein will be apparent to those skilled in the art from the following description. According to an embodiment, there is provided a module board including a plurality of stacked layers including first to nth layers, first to kth module clock signal terminals disposed in an assembly region of at least one of an upper surface of the first layer and a lower surface of the nth layer at a first predetermined interval, kth+1 module clock signal terminals to kth module clock signal terminals disposed in the assembly region at a second predetermined interval, first to kth module clock signal terminals disposed adjacent to the kth module clock signal terminals, second terminating resistor terminals disposed adjacent to the kth module clock signal terminals, a plurality of terminals disposed in a terminal region of the at least one surface and including a clock signal terminal, first to kth module clock signal terminals disposed in the assembly region at a second predetermined interval, first to kth+1 module clock signal terminals disposed in the first to kth module clock signal terminals, first to branch lines for connecting the first to the first signal terminals, and branch lines for connecting the first to the first signal terminals, the fourth signal line is used for sequentially connecting the k+1th module clock signal terminal to the 2k module clock signal terminal with the second terminating resistor terminal, wherein the length of the third signal line is greater than the sum of the length of the first signal line and the length of the second signal line. According to an embodiment, there is provided a memory module including a module board. The module board includes a plurality of stacked layers including first to nth layers; first to kth module clock signal terminals arranged in a component area of at least one of an upper surface of the first layer and a lower surface of the nth layer at a first predetermined interval; a k+1th module clock signal terminal to a 2k module clock signal terminal, the k+1th module clock signal terminal to the 2k module clock signal terminal being arranged in the assembly region at a second predetermined interval, a first termination resistor terminal provided adjacent to the k module clock signal terminal, a first termination resistor connected to the first termination resistor terminal, a second termination resistor terminal provided adjacent to the 2k module clock signal terminal, a second termination resistor connected to the second termination resistor terminal, a plurality of terminals arranged in an end region of the at least one surface and including a clock signal terminal, a first branch line for connecting the clock signal terminal provided on the at least one surface to a first branch point, a first signal line