CN-114512479-B - Semiconductor structure and forming method thereof

Abstract

A semiconductor structure comprises a substrate, a grid structure, source-drain doped layers, a source-drain laminated layer and a source-drain laminated layer, wherein the grid structure is arranged on the substrate and parallel to the surface of the substrate, the extending direction of the grid structure is transverse, the extending direction of the grid structure is vertical, the source-drain doped layers are arranged in the substrate on two sides of the grid structure, and the source-drain laminated layer is arranged on the source-drain doped layers and comprises a source-drain plug and a source-drain interconnection structure which is vertical to the source-drain plug. In the embodiment of the invention, the source-drain lamination comprises the source-drain plug and the source-drain interconnection structure standing on the source-drain plug, that is to say, the source-drain plug and the source-drain interconnection structure are of an integrated structure, the adhesiveness between the source-drain interconnection structure and the source-drain plug is strong, the corresponding strength is high, and the on-resistance between the source-drain interconnection structure and the source-drain plug is small because the source-drain interconnection structure and the source-drain plug are of an integrated structure, thereby being beneficial to reducing the power consumption of a semiconductor structure, improving the current characteristic and optimizing the electrical property of the semiconductor structure.

Inventors

• WANG NAN

Assignees

• 中芯国际集成电路制造(上海)有限公司
• 中芯国际集成电路制造(上海)有限公司
• 中芯国际集成电路制造(北京)有限公司
• 中芯国际集成电路制造(北京)有限公司

Dates

Publication Date

20260421

Application Date

20201116

Priority Date

20201116

Claims (20)

1. 1. A semiconductor structure, comprising: a substrate; The grid structure is positioned on the substrate and parallel to the surface of the substrate, the extending direction of the grid structure is transverse, and the extending direction of the grid structure is vertical; the source-drain doping layers are positioned in the substrate at two sides of the grid structure; a source-drain lamination layer positioned on the source-drain doping layers, wherein the source-drain lamination layer comprises a source-drain plug and a source-drain interconnection structure standing on the source-drain plug; The semiconductor structure comprises a gate plug, a gate electrode and a gate electrode, wherein the gate plug is erected on the gate electrode structure; And the protection layer is positioned on the lateral side wall of the source-drain interconnection structure and the longitudinal side wall of the grid plug.
2. 2. The semiconductor structure of claim 1, wherein the protective layer is further on top of the source drain plug.
3. 3. The semiconductor structure of claim 1, wherein the material of the protective layer comprises one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbide, silicon carbonitride, aluminum nitride, and aluminum oxide.
4. 4. The semiconductor structure of claim 1, wherein the protective layer has a thickness of 2 nm to 6 nm.
5. 5. The semiconductor structure of claim 1, wherein the source drain plug comprises a conductive layer and a barrier layer at a bottom and longitudinal sidewalls of the conductive layer; The source-drain interconnection structure comprises the conductive layer and the blocking layer positioned on the longitudinal side wall of the conductive layer.
6. 6. The semiconductor structure of claim 1, wherein the semiconductor structure comprises a first dielectric layer on the gate structure on a side of a gate plug; the semiconductor structure further comprises a second dielectric layer which is positioned on the source-drain plug at the side part of the source-drain interconnection structure.
7. 7. The semiconductor structure of claim 1, wherein the substrate comprises: A substrate; a fin portion separated from the substrate; and the isolation layer is positioned on the substrate at the side part of the fin part and covers part of the side wall of the fin part.
8. 8. A method of forming a semiconductor structure, comprising: providing a substrate, wherein a grid structure is formed on the substrate, and source drain doping layers are formed in the substrate at two sides of the grid structure; Forming a source-drain lamination layer on the source-drain doping layers, wherein the source-drain lamination layer comprises a source-drain plug connected with a plurality of source-drain doping layers between the grid structures and a source-drain interconnection structure standing on the source-drain plug; The method for forming the semiconductor structure comprises the steps of forming a first dielectric layer on the gate structure after providing a substrate and before forming the source-drain lamination; The method for forming the semiconductor structure further comprises the steps of forming a protective layer on the source-drain interconnection structure, the side wall of the first dielectric layer and the top of the source-drain plug after forming the first dielectric layer, etching the first dielectric layer between the protective layers to form a groove exposing the gate structure, and forming a gate plug in the groove.
9. 9. The method of forming a semiconductor structure of claim 8, wherein in the step of providing a substrate, an interlayer dielectric layer is formed on the substrate on which the gate structure is exposed, the interlayer dielectric layer covering sidewalls of the gate structure; forming a first dielectric material layer on the interlayer dielectric layer and the gate structure; etching the first dielectric material layer and the interlayer dielectric layer to form source and drain openings exposing the source and drain doping layers, wherein the rest of the first dielectric material layer positioned at the top of the gate structure is used as the first dielectric layer; Forming a source-drain plug connecting a plurality of source-drain doped layers and a source-drain interconnection structure standing on the source-drain plug between the gate structures, wherein the step of forming a first metal layer in the source-drain opening; And etching the first metal layer to form the source-drain plug and a source-drain interconnection structure standing on the source-drain plug.
10. 10. The method of claim 9, wherein the first dielectric material layer and the interlayer dielectric layer are etched using a dry etching process to form source and drain openings exposing the source and drain doped layers.
11. 11. The method of forming a semiconductor structure of claim 9, wherein forming said first metal layer comprises conformally covering a barrier material layer in said source drain openings, and forming a conductive material layer on said barrier material layer exposed by said source drain openings, said barrier material layer and said conductive material layer being said first metal layer.
12. 12. The method of forming a semiconductor structure of claim 9, wherein the first metal layer is etched using a dry etching process to form the source drain plug and a source drain interconnect structure that is upstanding from the source drain plug.
13. 13. The method of forming a semiconductor structure of claim 8, wherein the material of the protective layer comprises one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbide, silicon carbonitride, aluminum nitride, and aluminum oxide.
14. 14. The method of forming a semiconductor structure of claim 8, wherein the protective layer has a thickness of 2 nm to 6 nm.
15. 15. The method of forming a semiconductor structure of claim 8, wherein the step of forming the protective layer comprises: forming a protective material layer which conformally covers the source drain plug and the source drain interconnection structure positioned on the source drain plug; And removing the protective material layer on the top of the first dielectric layer, and taking the rest of the protective material layer on the side walls of the source-drain interconnection structure and the first dielectric layer and the top of the source-drain plug as a protective layer.
16. 16. The method of claim 15, wherein the protective material layer is formed by atomic layer deposition or chemical vapor deposition.
17. 17. The method of claim 15, wherein the protective material layer on top of the first dielectric layer is removed using a planarization process.
18. 18. The method of forming a semiconductor structure of claim 15, further comprising forming a second dielectric layer over said source-drain interconnect structure exposing said source-drain plug after forming said protective material layer and before forming said protective layer.
19. 19. The method of forming a semiconductor structure of claim 8, wherein the first dielectric layer between the protective layers is etched using a dry etching process to form recesses exposing the gate structure.
20. 20. The method of claim 8, wherein the first dielectric layer between the protective layers is etched to form a recess exposing the gate structure, the protective layer having a greater difficulty than the first dielectric layer; And etching the first dielectric layer between the protective layers to form a groove exposing the gate structure, and etching the gate cap layer, wherein the etching difficulty of the protective layer is greater than that of the gate cap layer.

Description

Semiconductor structure and forming method thereof Technical Field Embodiments of the present disclosure relate to semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same. Background With the continued development of integrated circuit fabrication technology, the demands on the degree of integration and performance of integrated circuits are becoming ever higher. In order to improve the integration level and reduce the cost, the critical dimensions of the components are continuously reduced, and the circuit density inside the integrated circuit is increasingly high, so that the wafer surface cannot provide enough area to manufacture the required interconnection line. In order to meet the requirements of the interconnect lines with reduced critical dimensions, the different metal layers or the conduction between the metal layers and the substrate is realized through the interconnect structure. The interconnect structure includes an interconnect line and a contact hole plug formed within the contact opening. The contact hole plugs are connected with the semiconductor device, and the interconnection lines realize the connection between the contact hole plugs, so that a circuit is formed. The contact hole plug in the transistor structure comprises a gate plug positioned at the top of the gate structure and used for realizing the connection between the gate structure and an external circuit, and further comprises a source-drain plug positioned at the top of the source-drain doped layer and a source-drain interconnection structure used for realizing the connection between the source-drain doped layer and the external circuit, wherein the formation quality of the gate plug, the source-drain plug and the source-drain interconnection structure is positively related to the performance of the semiconductor structure. Disclosure of Invention The embodiment of the invention solves the problem of providing a semiconductor structure and a forming method thereof, so that a grid plug, a source drain interconnection structure and a source drain plug are not easy to bridge, and the electrical property of the semiconductor structure is optimized. In order to solve the problems, the embodiment of the invention provides a semiconductor structure, which comprises a substrate, a grid structure, a source-drain doped layer, a source-drain laminated layer and a plurality of source-drain doped layers, wherein the grid structure is positioned on the substrate and parallel to the surface of the substrate, the extending direction of the grid structure is transverse, the extending direction of the grid structure is vertical to the extending direction of the grid structure, the source-drain doped layer is positioned in the substrate at two sides of the grid structure, and the source-drain laminated layer comprises a source-drain plug and a source-drain interconnection structure standing on the source-drain plug. Correspondingly, the embodiment of the invention also provides a method for forming the semiconductor structure, which comprises the steps of providing a substrate, forming a grid structure on the substrate, forming source and drain doping layers in the substrate at two sides of the grid structure, and forming a source and drain lamination layer on the source and drain doping layers, wherein the source and drain lamination layer comprises a source and drain plug connected with a plurality of source and drain doping layers between the grid structures and a source and drain interconnection structure standing on the source and drain plug. Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages: The semiconductor structure provided by the embodiment of the invention comprises a substrate, a grid structure, a source-drain doped layer, a source-drain laminated layer and a plurality of source-drain laminated layers, wherein the grid structure is positioned on the substrate and parallel to the surface of the substrate, the extending direction of the grid structure is transverse, the extending direction of the grid structure is vertical, the source-drain doped layer is positioned in the substrate at two sides of the grid structure, and the source-drain laminated layer comprises a source-drain plug and a source-drain interconnection structure standing on the source-drain plug. In the embodiment of the invention, the source-drain lamination comprises the source-drain plug and the source-drain interconnection structure standing on the source-drain plug, that is to say, the source-drain plug and the source-drain interconnection structure are of an integrated structure, compared with the case that the source-drain plug and the source-drain interconnection structure are separated, the source-drain interconnection structure and the source-drain plug have stronger adhesiveness and higher corresponding strength, and the source-drain i