CN-114513116-B - Shutdown protection circuit, shutdown protection method and self-powered system

CN114513116BCN 114513116 BCN114513116 BCN 114513116BCN-114513116-B

Abstract

The invention discloses a shutdown protection circuit, which is characterized in that a sampling comparison circuit is coupled with a logic circuit, a feedback comparison circuit is also coupled with the logic circuit, the logic circuit is coupled with an RS trigger, and the logic circuit processes output signals of the sampling comparison circuit and the feedback comparison circuit and then controls current leakage of an auxiliary winding to the output end of the RS trigger. The invention also discloses a shutdown protection method, which comprises the steps of detecting a feedback voltage and a sampling voltage, and when the duration of detecting that the feedback voltage is larger than the second voltage for a first delay time and the sampling voltage is smaller than a sampling threshold voltage, discharging the starting current of an auxiliary winding for supplying power to the working voltage, so that the system enters a shutdown mode. The invention can lead the working voltage to discharge the discharge current under the specific condition, thereby accelerating the power failure of the working voltage.

Inventors

JIN WEIXIANG
HU CHANGWEI
ZHU XIANGWEN

Assignees

深圳市必易微电子股份有限公司

Dates

Publication Date: 20260512
Application Date: 20220217

Claims (8)

1. The shutdown protection circuit is characterized by comprising a sampling comparison circuit, a logic circuit, a feedback comparison circuit and an RS trigger; the sampling comparison circuit is coupled with the logic circuit, the feedback comparison circuit is also coupled with the logic circuit, and the logic circuit is coupled with the RS trigger; The sampling comparison circuit compares the acquired sampling voltage with a sampling threshold voltage and then outputs a third output signal; the feedback comparison circuit compares the acquired feedback voltage with the second voltage and outputs a fourth output signal; the first delay circuit is coupled between the sampling comparison circuit and the logic circuit, and is used for delaying the third output signal for a first delay time and then outputting the first output signal to the logic circuit; the second delay circuit is coupled to the output end of the feedback comparison circuit and is used for outputting a second output signal after performing delay processing on the fourth output signal for a second delay time; the first delay time is smaller than the second delay time, the second delay time is equal to the duration of a debounce period of an OLP protection, and the second output signal is used for representing the end of the debounce period and the start of the OLP protection; the logic circuit outputs a processing result to the input end of the RS trigger after performing logic operation processing on the third output signal and the fourth output signal, the output end of the RS trigger controls current discharge of an auxiliary winding, and the auxiliary winding is used for supplying power to working voltage.
2. The shutdown protection circuit of claim 1, wherein the logic circuit comprises a first logic gate coupled to a first input of the RS flip-flop, the first logic gate performing an and operation on the first output signal and the inverted fourth output signal and outputting the result to the RS flip-flop; The second input end of the RS trigger is coupled with the feedback comparison circuit and acquires the fourth output signal.
3. The shutdown protection circuit of claim 2, wherein the logic circuit further comprises a second logic gate coupled to the second input of the RS flip-flop, wherein the second logic gate is electrically coupled to the fourth output signal, the second output signal, and an under-voltage lock signal for indicating that the system is in an under-voltage lock state, and outputs the third output signal, the second output signal, and the under-voltage lock signal to the RS flip-flop after performing a three-input or gate operation.
4. A shutdown protection method based on the shutdown protection circuit as claimed in any one of claims 1 to 3, comprising The shutdown signal is input, the working voltage starts to drop, and the OLP protection is triggered and waits for a debounce period; detecting feedback voltage and sampling voltage; upon detecting that the feedback voltage is greater than a second voltage, timing a duration that the feedback voltage is greater than the second voltage; When the duration of the feedback voltage which is greater than the second voltage is counted for a first delay time and the sampling voltage is detected to be smaller than the sampling threshold voltage, the starting current of an auxiliary winding supplying power to the working voltage is discharged, and the system enters a shutdown mode, wherein the first delay time is smaller than the duration of the debounce period.
5. The shutdown protection method of claim 4, further comprising And when the duration time for timing the feedback voltage to be larger than the second voltage is longer than a second delay time, stopping current of the auxiliary winding is discharged, and the system exits from a shutdown mode, wherein the second delay time is larger than the first delay time, and the second delay time is equal to the duration time of the debounce period.
6. The shutdown protection method of claim 5, further comprising And when the feedback voltage is detected to be smaller than the second voltage, stopping current discharge of the auxiliary winding, and exiting the shutdown mode.
7. The shutdown protection method of claim 6, further comprising When the working voltage is reduced to be lower than the third voltage, the system enters an under-voltage locking state, the stopping current of the auxiliary winding is discharged, and the system exits from a shutdown mode.
8. A self-powered system comprising a shutdown protection circuit as claimed in any one of claims 1 to 3.

Description

Shutdown protection circuit, shutdown protection method and self-powered system Technical Field The present invention relates to the field of electronic information, and in particular, to a shutdown protection circuit, a shutdown protection method, and a self-powered system. Background In the typical SSR secondary feedback field, OLP exists as a core indicator of system performance. The OLP protection is used for monitoring a line in real time, and automatically closing a main power switch tube when an abnormality is monitored, so that a protection effect is achieved. Therefore, protection involving OLP is also a necessary condition for SSR IC circuits. In traditional applications, the OLP protection generally does not cause additional OLP error protection problems in the system, because the protection mode of the OLP protection is directly hooked with the output voltage, regardless of the input energy, when the optocoupler feedback voltage is continuously higher than a certain threshold value when SSR Low Side is connected or is continuously lower than a certain threshold value when SSR HIGH SIDE is connected, and after a debounce period t_debounce is continued, the OLP protection system stops the Switch (i.e. turns off the main power Switch tube), and then enters a restart phase. In a typical VDD RC starting system, as shown in fig. 1, since OLP protection is performed after the Switch is stopped, the system needs to perform UVLO reset (UVLO is abbreviated as "under-voltage lock") and in the process of UVLO reset, the working voltage VDD will be powered down, and the reset starting time is long. Therefore, in the process of resetting the UVLO, the condition of OLP error protection caused by fast startup and shutdown cannot occur, namely the system does not respond to input fast change in the restarting stage. In a typical high voltage self-powered SSR system, as shown in fig. 2. As the SSR IC circuitry is converted from a typical VDD RC start system to a high voltage self-powered system, the OLP protected restart logic cannot use the original ULVO clear restart mode any more. This is because VDD for high voltage self-powered systems is constantly supplied by JEFT-tubing and stabilizes at a constant value. Therefore, the OLP protection logic designed in the existing high-voltage self-powered system is generally expressed in the following sequence (1) entering the output overload state, (2) maintaining more than one debounce period t_debounce, (3) triggering the OLP protection (while VDD is stabilized at a constant value), (4) timing a certain time as the delay time t_delay of the OLP protection, (5) entering the start-up restart of the system, and all protection is cleared (i.e. the OLP protection is stopped). When the OLP protection is triggered due to the overload of the output and VDD is stabilized at a constant value, the OLP protection delay is caused, and after the OLP protection delay is finished, the system enters into normal start-up restart. In a high-voltage self-powered system, FB is kept high to trigger the logic of the OLP protection, but because insufficient input energy can lead to FB to be pulled high in a shutdown mode, the judgment condition that the FB is pulled high to trigger the OLP protection is not the only condition, if the logic of the OLP protection is triggered in the shutdown mode, and the auxiliary winding supply charges are enough to maintain VDD for a long time (> T_debounce) so that the system does not drop to UVLO, the system can enter an OLP protection Delay state (namely an OLP Delay state, the OLP protection time is prolonged) due to the fact that normal shutdown is not carried out along with the input AC OFF and BUS energy drop, and the Delay time of the OLP protection Delay is long. In this state, the fast power on/off will be freed from the response. Because the IC is not turned on in response to the input during the OLP protection delay, the system cannot respond to the output in time, and therefore the advantage of ultra-fast start-up as high-voltage self-power is lost. When the OLP protection is triggered in the shutdown mode and VDD is stabilized at a constant value, the OLP protection delay is also caused, but the delay time of the OLP protection delay is longer, so that the system cannot enter into the fast startup. Therefore, the OLP protection delay in this case is the case of OLP false protection. As set forth above, the prior art has no clear way of determining whether to distinguish between shutdown-triggered OLP protection and overload-triggered OLP protection. In addition, the prior art typically leaks VDD charge more by lengthening the OLP protection Debounce period (OLP Debounce time), so that UVLO reset is performed as soon as possible after AC OFF, which is a serious limitation. Because the difference in configuration capacitance and load of the peripheral auxiliary winding requires that the minimum OLP Debounce time of the system be much higher tha