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CN-114518940-B - Task scheduling circuit, method, electronic device and computer readable storage medium

CN114518940BCN 114518940 BCN114518940 BCN 114518940BCN-114518940-B

Abstract

The embodiment of the disclosure discloses a task scheduling circuit, a task scheduling method, electronic equipment and a computer readable storage medium. The task scheduling circuit comprises a core resource storage circuit, a task packet scheduling circuit and a control circuit, wherein the core resource storage circuit is used for storing state information and calculation power levels of each processing core, the task packet scheduling circuit is used for acquiring a task packet of a task to be executed, the task packet comprises at least one task instruction of the same task and calculation power requirements of the task packet, an idle processing core is confirmed from the core resource storage circuit according to the calculation power levels and the calculation power requirements, the task packet is sent to the idle processing core, and the control circuit is used for receiving the state information of the idle processing core and indicating the task packet scheduling circuit to work according to the state information. The task scheduling circuit schedules task packets through the state information and the computational power level of the processing core, and solves the technical problem of low scheduling efficiency in the prior art.

Inventors

  • Request for anonymity

Assignees

  • 北京希姆计算科技有限公司

Dates

Publication Date
20260505
Application Date
20201119

Claims (10)

  1. 1. A task scheduling circuit for use in a system including at least two processing cores, comprising: A core resource storage circuit, a task packet scheduling circuit and a control circuit, wherein, The core resource storage circuit is used for storing state information and calculation power level of each processing core; The task package scheduling circuit is used for acquiring a task package to be executed, wherein the task package comprises at least one task instruction of the same task and the calculation force requirement of the task package; the task package is sent to the idle processing core, and the idle processing core is used for continuously executing at least one task instruction in the task package; and the control circuit is used for receiving the state information of the idle processing core and indicating the task packet scheduling circuit to work according to the state information.
  2. 2. The task scheduling circuit of claim 1, wherein the core resource storage circuit for storing state information and computational power levels for each of the processing cores comprises: The core resource storage circuit is used for storing a core resource table and a computing power level corresponding to the core resource table, wherein the core resource table comprises a processing core identifier and a processing core state bit corresponding to the processing core identifier, and the processing core state bit is used for representing an idle state or a busy state.
  3. 3. The task scheduling circuit according to claim 2, wherein the core resource storage circuit is configured to store a computing power index table and a plurality of core resource tables, wherein computing power levels assigned to processing cores in different core resource tables are different, computing power levels assigned to processing cores in a same core resource table are identical, the computing power levels are identical or similar, and the computing power index table is configured to indicate computing power levels corresponding to the core resource tables.
  4. 4. A task scheduling circuit according to claim 3, wherein the control circuit is operable to instruct the task packet scheduling circuit to operate in accordance with the status information, comprising: When the state information of each processing core belonging to the same core resource table is busy, the control circuit is used for indicating the task packet scheduling circuit not to execute reading of the core resource table according to the state information; when the state information of any processing core belonging to the same core resource table is in idle state, the control circuit is used for indicating the task packet scheduling circuit to continuously receive the subsequent task packet according to the state information, or, And when the state information of each processing core is in a busy state, the control circuit indicates the task packet scheduling circuit to enter a waiting state according to the state information.
  5. 5. The task scheduling circuit of any one of claims 1-4, wherein the task packet scheduling circuit is further configured to: modifying state information of the idle processing cores in the core resource storage circuit, and sending the state information to the control circuit.
  6. 6. The task scheduling circuit of claim 5, wherein the task packet scheduling circuit to modify status information of the idle processing cores in the core resource storage circuit and send the status information to the control circuit comprises: After the idle processing core executes the task package, modifying the state information of the idle processing core in the core resource storage circuit to be in an idle state, or Before or after the task packet is sent to the idle processing core, modifying the state of the idle processing core to be a busy state.
  7. 7. The task scheduling circuit of claim 6, wherein the control circuit is further configured to: state information of the processing cores stored in the control circuit is modified.
  8. 8. The task scheduling circuit of any one of claims 1-4, wherein the task scheduling circuit further comprises: The task instruction cache circuit comprises task instruction cache queues corresponding to the processing cores one by one, and each member in the task packet cache queues is used for caching task instructions in the task packets of the corresponding processing cores.
  9. 9. The task scheduling circuit of any one of claims 1 to 4, wherein the task package includes a task number of the task package, a task package number, a computational power requirement of the task package, and at least one task instruction.
  10. 10. A task scheduling method for a task scheduling circuit according to any one of claims 1 to 9, comprising: Acquiring a task package to be executed, wherein the task package comprises at least one task instruction of the same task and the calculation force requirement of the task package; Confirming an idle processing core according to the calculation power demand of the task package and the calculation power level of the at least two processing cores, wherein the idle processing core is used for continuously executing at least one task instruction in the task package; Sending the task packet to the idle processing core; and indicating the scheduling process of the task package according to the state information of the idle processing core.

Description

Task scheduling circuit, method, electronic device and computer readable storage medium Technical Field The present disclosure relates to the field of processors, and in particular, to a task scheduling circuit, a task scheduling method, an electronic device, and a computer readable storage medium. Background With the development of science and technology, human society is rapidly entering the intelligent era. The important characteristics of the intelligent age are that the variety of data obtained by people is more and more, the amount of obtained data is more and more, and the requirement on the speed of processing the data is higher and more. Chips are the cornerstone of task scheduling, which fundamentally determines people's ability to process data. From the application field, the chip mainly has two routes, namely a general chip route, such as CPU (Central Processing Unit), which can provide great flexibility but has lower effective calculation force when processing algorithms in specific fields, and a special chip route, such as TPU (Tensor Processing Unit), which can exert higher effective calculation force in specific fields but faces the flexible and changeable more general fields, and has poorer processing capability and even cannot be processed. Because of the large variety and huge number of data in the intelligent age, the chip is required to have extremely high flexibility, can process algorithms in different fields and in daily life and in a very strong processing capacity, and can rapidly process extremely large and rapidly growing data volume. In neural network computing, multi-core or many-core chips are often used. The cores in the multi (many) core architecture have certain independent processing capacity and have relatively large in-core storage space for storing programs, data and weights of the cores. How to make many cores capable of efficiently performing calculation is a key to determining the performance of the whole chip. The computational effort of each core depends on a number of factors, such as the scheduling and allocation of tasks, the architecture of the chip, the structure of the core, the circuitry of the core, etc. The scheduling and the distribution of the tasks are a very critical factor, if the scheduling and the distribution of the tasks are reasonable, the effective calculation force of each core can be fully exerted, otherwise, the effective calculation force of each core can be lowered. The following schemes are generally used in the prior art to schedule processing core tasks: A scheme for task scheduling using a scheduler is shown in fig. 1. In this scenario, the scheduler receives instructions from the instruction source and then transmits the instructions to the processing cores in a policy, e.g., order, that each process checks different data to execute the same instructions. Each processing core may be a relatively simple structure such as SIMD (Single Instruction Multiple Data, single instruction multiple data structure) with shared control circuitry and registers, or a relatively complex structure with some autonomy such as SIMT (Single Instruction Multiple Threads, single instruction multiple thread) with independent control circuitry and registers. However, the scheme is generally used for instruction level scheduling, only one or a few instructions can be scheduled at a time, when a relatively large task needs to be completed, frequent scheduling is needed, and scheduling efficiency is reduced. Disclosure of Invention This summary is provided to introduce a selection of concepts in a simplified form that are further described below in the detailed description. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter. In order to solve the technical problems of inflexible task scheduling and complicated control of a processing core in the prior art, the embodiment of the disclosure provides the following technical scheme: in a first aspect, an embodiment of the present disclosure provides a task scheduling circuit, including: A core resource storage circuit, a task packet scheduling circuit and a control circuit, wherein, The core resource storage circuit is used for storing state information and calculation power level of each processing core; The task package scheduling circuit is used for receiving a task package of a task to be executed, wherein the task package comprises at least one task instruction of the same task and a calculation power demand of the task package; and the control circuit is used for receiving the state information of the idle processing core and indicating the task packet scheduling circuit to work according to the state information. Further, the core resource storage circuitry is configured to store a state and a computing power level of each of the processing cores, and includes: The core resource