CN-114531151-B - Phase-locked loop, method for generating periodic output waveform and clock generating circuit

Abstract

A phase locked loop including a phase/frequency detector, a charge pump, an oscillator, and a realignment path is provided. The phase/frequency detector is used for receiving the reference signal and the feedback signal. The charge pump is used for receiving the output from the phase/frequency detector and generating pulses. The oscillator is used for generating an output waveform based on the charge pump pulses. The realignment path is configured to generate a clock realignment signal provided to the oscillator based on the outputs from the phase/frequency detector.

Inventors

• CAI ZONGXIAN
• SHEN RUIBIN
• ZHANG ZHIXIAN
• XIE ZHENGXIANG

Assignees

• 台湾积体电路制造股份有限公司

Dates

Publication Date

20260508

Application Date

20210414

Priority Date

20210127

Claims (20)

1. 1. A phase locked loop comprising: a phase/frequency detector for receiving a reference signal and a feedback signal; a charge pump for receiving the first and second outputs from the phase/frequency detector and generating a plurality of pulses; an oscillator for generating an output waveform based on the plurality of pulses of the charge pump; a filter between the charge pump and the oscillator, and A realignment path to generate a clock realignment signal provided to the oscillator after the third output from the charge pump bypasses the filter and is routed through a third match gate based on a third output from the charge pump.
2. 2. The phase locked loop of claim 1, wherein the charge pump comprises a first match gate and a second match gate.
3. 3. The phase locked loop of claim 2, wherein the first, second, and third match gates are all or gates.
4. 4. A phase locked loop as claimed in claim 1, wherein, The filter is a low pass filter that is used to receive the plurality of pulses from the charge pump and to generate an input to the oscillator.
5. 5. The phase locked loop of claim 1, wherein the clock realignment signal is periodically generated to reset any accumulated error in the phase locked loop.
6. 6. A phase locked loop as claimed in claim 1, wherein the realignment path does not receive input from before the phase/frequency detector.
7. 7. The phase locked loop of claim 1, wherein the realignment path does not include a programmable delay line or a delay locked loop.
8. 8. The phase locked loop of claim 1, further comprising: A feedback path providing the output waveform as the feedback signal to the phase/frequency detector.
9. 9. A phase locked loop as claimed in claim 8, wherein the feedback path comprises a frequency divider.
10. 10. The phase locked loop of claim 1 wherein the reference signal is provided to the phase/frequency detector after a first delay period, wherein the delay period is determined by an automatic placement and routing routine of computer aided circuit design software.
11. 11. The phase locked loop of claim 10 wherein said charge pump receives said first output and said second output from said phase/frequency detector after a second delay period, wherein said second delay period is selectable by a user using said computer aided circuit design software.
12. 12. The phase locked loop of claim 1, wherein the realignment path comprises: a pulse generator, wherein the realignment signal is generated by the pulse generator, the clock realignment signal being provided to the oscillator.
13. 13. A phase locked loop as claimed in claim 12, wherein a pulse width of said realignment signal is controllable via an input to said pulse generator.
14. 14. The phase-locked loop of claim 13 wherein the pulse width of the pulse generator is controlled to have a length that is shorter than a width of a pulse generated by the phase/frequency detector and a length that is half-shorter than a period of the output waveform.
15. 15. The phase locked loop of claim 13 wherein the input selects one of a plurality of sequential logic gates providing a select signal, wherein each of the plurality of sequential logic gates is associated with a different pulse width of the realignment signal.
16. 16. A method of generating a periodic output waveform, comprising the steps of: comparing the phase and frequency of a reference signal and a feedback signal using a phase/frequency detector; generating a plurality of pulses based on the first output and the second output of the phase/frequency detector using a charge pump; generating an output waveform based on the plurality of pulses of the charge pump and a clock realignment signal based on a third output from the charge pump, and The third output from the charge pump is provided to a first alignment logic gate such that the third output bypasses a filter prior to generating the clock realignment signal.
17. 17. The method of claim 16, further comprising the step of: each of the first and second outputs of the phase/frequency detector is provided to respective second and third alignment logic gates prior to use in generating the plurality of pulses.
18. 18. The method of claim 17, wherein the first alignment logic gate, the second alignment logic gate, and the third alignment logic gate are normal type logic gates.
19. 19. A clock generation circuit, comprising: A charge pump for receiving a first input signal and a second input signal, the charge pump for routing the first input signal and the second input signal to a corresponding first alignment logic gate and a second alignment logic gate, the charge pump for generating a plurality of pulse signals and output signals based on the first input signal and the second input signal; a realignment circuit for generating a realignment signal based on the output signal from the charge pump after bypassing a filter and routing the output signal from the charge pump through a third alignment logic gate, and An oscillator for generating an output waveform based on the plurality of pulse signals and the realignment signal.
20. 20. The clock generation circuit of claim 19, wherein the first alignment logic gate, the second alignment logic gate, and the third alignment logic gate are normal type logic gates.

Description

Phase-locked loop, method for generating periodic output waveform and clock generating circuit Technical Field The present disclosure relates to a phase locked loop, and more particularly to a phase locked loop for generating a circuit clock. Background High-speed clock signals have a variety of applications, including wireless data communications and medical devices and instruments. A phase locked loop (phase locked loop, PLL) is a device typically implemented to lock the phase and frequency of a first device, typically a higher frequency local oscillator device such as a voltage controlled oscillator (voltage controlled oscillator, VCO), to a second device, typically a lower frequency reference device such as a temperature compensated (temperature compensated, TCXO) or oven controlled oscillator (oven controlled oscillator, OCXO). The PLL is utilized because the phase and frequency of a first device (typically a higher frequency device) may not be very stable in temperature and time, while a second device performs better with respect to these characteristics. Disclosure of Invention According to one embodiment of the present disclosure, a phase locked loop is disclosed that includes a phase/frequency detector, a charge pump, an oscillator, a filter, and a realignment path. The phase/frequency detector is used for receiving the reference signal and the feedback signal. The charge pump is used for receiving the first output and the second output from the phase/frequency detector and generating pulses. The oscillator is used for generating an output waveform based on the charge pump pulse. The filter is between the charge pump and the oscillator. The realignment path is to generate a clock realignment signal provided to the oscillator after bypassing the filter and routing through the first match gate based on the third output from the charge pump. In accordance with another embodiment of the present disclosure, a method of generating a periodic output waveform is disclosed that includes comparing a phase and frequency of a reference signal and a feedback signal using a phase/frequency detector, generating pulses based on a first output and a second output of the phase/frequency detector using a charge pump, generating an output waveform based on the charge pump pulses and a clock realignment signal, the clock realignment signal being based on a third output from the charge pump, and providing the third output from the charge pump to a first alignment logic gate such that the third output bypasses a filter prior to generating the clock realignment signal. According to another embodiment of the present disclosure, a clock generation circuit is disclosed, comprising a charge pump, a realignment circuit, and an oscillator. The charge pump is used for receiving the first input signal and the second input signal, the charge pump is used for routing the first input signal and the second input signal to the corresponding first alignment logic gate and the second alignment logic gate, and the charge pump is used for generating a pulse signal and an output signal based on the first input signal and the second input signal. A realignment circuit is to generate a realignment signal based on the output signal from the charge pump after bypassing a filter and routing the output signal from the charge pump through a third alignment logic gate. The oscillator is used for generating an output waveform based on the pulse signal and the realignment signal. According to one embodiment of the present disclosure, a phase locked loop is disclosed that includes a charge pump, an oscillator, a filter, and a realignment path. The filter is between the charge pump and the oscillator. The realignment path generates a clock realignment signal that is provided to the oscillator. The clock realignment signal is based on the first output from the charge pump after bypassing the filter and routing through a first match gate. In accordance with another embodiment of the present disclosure, a method of generating a periodic output waveform is disclosed that includes generating a clock realignment signal based on an output from a charge pump, and providing the output from the charge pump to a first alignment logic gate such that the output bypasses a filter prior to generating the clock realignment signal. According to another embodiment of the present disclosure, a clock generation circuit is disclosed, comprising a charge pump, a realignment circuit, and an oscillator. The charge pump receives an input signal to generate an output signal based on the output signal and generates a plurality of pulse signals after the output signal is routed through the first alignment logic gate based on the output signal. The realignment circuit generates a realignment signal based on the output signal after bypassing the filter and routing the output signal through the second alignment logic gate. The oscillator generates an output waveform based on the pu