CN-114546490-B - Apparatus, method, and system for hashing instructions

Abstract

The application discloses a device, a method and a system for hashing instructions. A processor includes a decoding circuit and an execution circuit. The decoding circuitry is to decode an instruction comprising at least one first field for 32-bit state elements A, B, C, D, E, F, G and H of a round according to the SM3 hash standard and at least one second field identifying an incoming message. The execution circuitry is to execute the decoded instructions to loop left shift the state element C, D, G, H by 9, 19 bits, respectively, to perform two rounds according to the SM3 hash standard on the input message, the state element A, B, the loop shifted state element C, D, the state element E, F, the loop shifted state element G, H to generate an updated state element A, B, E, F, and to store the updated state element A, B, E, F into a location specified by the instructions.

Inventors

• R. Shemi
• J. Aleuze
• I. Aneti
• Z. Spooper
• Feigerherry W.
• V. GOPAL
• A. Gredstin
• RUBANOVICH SIMON
• S. Gerre
• I Ai Erbu Rake spy
• J. Multidimentology

Assignees

• 英特尔公司

Dates

Publication Date

20260512

Application Date

20200303

Priority Date

20190329

Claims (20)

1. 1. A processor, comprising: Decoding circuitry for decoding a first instruction for computing an input message for a next round of hashing according to a SHA512 hashing standard, the first instruction comprising a plurality of fields for specifying a first vector register for storing a first 64-bit data element, a second 64-bit data element, a third 64-bit data element, and a fourth 64-bit data element, and a second vector register for storing a fifth 64-bit data element and a sixth 64-bit data element, and Execution circuitry coupled with the decode circuitry, the execution circuitry to perform operations corresponding to the first instruction, comprising: Generating a result, the result for comprising: A first 64-bit result element, the first 64-bit result element being equal to the first 64-bit data element added to a value equal to exclusive-or-XOR of the fifth 64-bit data element shifted right by nineteen bits in a round-robin fashion with the fifth 64-bit data element shifted right by sixty-one bits in a round-robin fashion with the fifth 64-bit data element shifted right by six bits in a right-shifting fashion; a second 64-bit result element, the second 64-bit result element being equal to the second 64-bit data element added to a value equal to the sixth 64-bit data element shifted right by nineteen bits in a round robin fashion xored with the sixth 64-bit data element shifted right by sixty one bits in a round robin fashion xored with the sixth 64-bit data element shifted right by six bits; A third 64-bit result element, the third 64-bit result element being equal to the third 64-bit data element added to a value equal to the first 64-bit result element shifted right by nineteen bits in a round robin fashion xored with the first 64-bit result element shifted right by sixty one bits in a round robin fashion xored with the first 64-bit result element shifted right by six bits; A fourth 64-bit result element, the fourth 64-bit result element being equal to the fourth 64-bit data element added to a value equal to the second 64-bit result element shifted right by nineteen bits in a round and the second 64-bit result element shifted right by sixty-one bits in a round and the second 64-bit result element shifted right by six bits in a round, and The result is stored in the first vector register.
2. 2. The processor of claim 1, wherein the fifth 64-bit data element and the sixth 64-bit data element are message elements according to the SHA512 hashing standard.
3. 3. The processor of claim 1, wherein the first instruction is one of two instructions for generating four SHA512 messages.
4. 4. The processor of claim 1, wherein the first 64-bit data element is to be stored in bits [63:0] of the first vector register, the second 64-bit data element is to be stored in bits [127:64] of the first vector register, the third 64-bit data element is to be stored in bits [191:128] of the first vector register, and the fourth 64-bit data element is to be stored in bits [255:192] of the first vector register.
5. 5. The processor of claim 1, wherein the execution circuitry is to store the first 64-bit result element in bits [63:0] of the first vector register, the second 64-bit result element in bits [127:64] of the first vector register, the third 64-bit result element in bits [191:128] of the first vector register, and the fourth 64-bit result element in bits [255:192] of the first vector register.
6. 6. The processor of claim 1, wherein the first vector register is a 256-bit vector register.
7. 7. The processor of claim 1, wherein the first vector register is a YMM register.
8. 8. The processor of claim 1, wherein the processor is a complex instruction set computing CISC processor.
9. 9. A method for instruction processing, comprising: decoding a first instruction for computing an input message for a next round of hashing according to a SHA512 hashing standard, the first instruction including a plurality of fields specifying a first vector register storing a first 64-bit data element, a second 64-bit data element, a third 64-bit data element, and a fourth 64-bit data element, and a second vector register storing a fifth 64-bit data element, a core sixth 64-bit data element, and Performing an operation corresponding to the first instruction, including: generating a result, the result comprising: A first 64-bit result element, the first 64-bit result element being equal to the first 64-bit data element added to a value equal to exclusive-or-XOR of the fifth 64-bit data element shifted right by nineteen bits in a round-robin fashion with the fifth 64-bit data element shifted right by sixty-one bits in a round-robin fashion with the fifth 64-bit data element shifted right by six bits in a right-shifting fashion; a second 64-bit result element, the second 64-bit result element being equal to the second 64-bit data element added to a value equal to the sixth 64-bit data element shifted right by nineteen bits in a round robin fashion xored with the sixth 64-bit data element shifted right by sixty one bits in a round robin fashion xored with the sixth 64-bit data element shifted right by six bits; A third 64-bit result element, the third 64-bit result element being equal to the third 64-bit data element added to a value equal to the first 64-bit result element shifted right by nineteen bits in a round robin fashion xored with the first 64-bit result element shifted right by sixty one bits in a round robin fashion xored with the first 64-bit result element shifted right by six bits; A fourth 64-bit result element, the fourth 64-bit result element being equal to the fourth 64-bit data element added to a value equal to the second 64-bit result element shifted right by nineteen bits in a round and the second 64-bit result element shifted right by sixty-one bits in a round and the second 64-bit result element shifted right by six bits in a round, and The result is stored in the first vector register.
10. 10. The method of claim 9, wherein the first 64-bit data element is to be stored in bits [63:0] of the first vector register, the second 64-bit data element is to be stored in bits [127:64] of the first vector register, the third 64-bit data element is to be stored in bits [191:128] of the first vector register, and the fourth 64-bit data element is to be stored in bits [255:192] of the first vector register.
11. 11. The method of claim 9 wherein storing the result in the first vector register comprises storing the first 64-bit result element in bits [63:0] of the first vector register, storing the second 64-bit result element in bits [127:64] of the first vector register, storing the third 64-bit result element in bits [191:128] of the first vector register, and storing the fourth 64-bit result element in bits [255:192] of the first vector register.
12. 12. The method of claim 9, wherein storing the result in the first vector register comprises storing the result in a 256-bit vector register.
13. 13. The method of claim 9 wherein storing the result in the first vector register comprises storing the result in a YMM register.
14. 14. A system for instruction processing, comprising: A non-transitory machine-readable storage medium storing code that, when executed by the system, causes the system to convert a first instruction of a first instruction set to one or more instructions of a second, different instruction set, the first instruction for computing an input message for a next round of hashing according to a SHA512 hashing standard, the first instruction comprising a plurality of fields for specifying a first vector register for storing a first 64-bit data element, a second 64-bit data element, a third 64-bit data element, and a fourth 64-bit data element, and a second vector register for storing a fifth 64-bit data element and a sixth 64-bit data element; a processor coupled with the non-transitory machine-readable storage medium, the processor for executing the one or more instructions of the second set of instructions to perform operations corresponding to the first instruction, comprising: Generating a result, the result for comprising: A first 64-bit result element, the first 64-bit result element being equal to the first 64-bit data element added to a value equal to exclusive-or-XOR of the fifth 64-bit data element shifted right by nineteen bits in a round-robin fashion with the fifth 64-bit data element shifted right by sixty-one bits in a round-robin fashion with the fifth 64-bit data element shifted right by six bits in a right-shifting fashion; a second 64-bit result element, the second 64-bit result element being equal to the second 64-bit data element added to a value equal to the sixth 64-bit data element shifted right by nineteen bits in a round robin fashion xored with the sixth 64-bit data element shifted right by sixty one bits in a round robin fashion xored with the sixth 64-bit data element shifted right by six bits; A third 64-bit result element, the third 64-bit result element being equal to the third 64-bit data element added to a value equal to the first 64-bit result element shifted right by nineteen bits in a round robin fashion xored with the first 64-bit result element shifted right by sixty one bits in a round robin fashion xored with the first 64-bit result element shifted right by six bits; A fourth 64-bit result element, the fourth 64-bit result element being equal to the fourth 64-bit data element added to a value equal to the second 64-bit result element shifted right by nineteen bits in a round and the second 64-bit result element shifted right by sixty-one bits in a round and the second 64-bit result element shifted right by six bits in a round, and The result is stored in the destination.
15. 15. The system of claim 14, wherein the fifth 64-bit data element and the sixth 64-bit data element are message elements according to a SHA512 hashing standard, and wherein the first instruction is one of two instructions for generating four SHA512 messages.
16. 16. The system of claim 14, wherein the first 64-bit data element is to be stored in bits [63:0] of the first vector register, the second 64-bit data element is to be stored in bits [127:64] of the first vector register, the third 64-bit data element is to be stored in bits [191:128] of the first vector register, and the fourth 64-bit data element is to be stored in bits [255:192] of the first vector register.
17. 17. The system of claim 14, wherein the processor is to store the first 64-bit result element in bits [63:0] of the destination, store the second 64-bit result element in bits [127:64] of the destination, store the third 64-bit result element in bits [191:128] of the destination, and store the fourth 64-bit result element in bits [255:192] of the destination.
18. 18. The system of claim 14, wherein the first vector register is a YMM register.
19. 19. A non-transitory machine-readable storage medium storing code, the code comprising first instructions that when executed by a machine cause the machine to perform a method comprising: Decoding the first instruction for computing an input message for a next round of hashing according to a SHA512 hashing standard, the first instruction including a plurality of fields specifying a first vector register storing a first 64-bit data element, a second 64-bit data element, a third 64-bit data element, and a fourth 64-bit data element, and a second vector register storing a fifth 64-bit data element and a sixth 64-bit data element, and Performing an operation corresponding to the first instruction, including: generating a result, the result comprising: A first 64-bit result element, the first 64-bit result element being equal to the first 64-bit data element added to a value equal to exclusive-or-XOR of the fifth 64-bit data element shifted right by nineteen bits in a round-robin fashion with the fifth 64-bit data element shifted right by sixty-one bits in a round-robin fashion with the fifth 64-bit data element shifted right by six bits in a right-shifting fashion; a second 64-bit result element, the second 64-bit result element being equal to the second 64-bit data element added to a value equal to the sixth 64-bit data element shifted right by nineteen bits in a round robin fashion xored with the sixth 64-bit data element shifted right by sixty one bits in a round robin fashion xored with the sixth 64-bit data element shifted right by six bits; A third 64-bit result element, the third 64-bit result element being equal to the third 64-bit data element added to a value equal to the first 64-bit result element shifted right by nineteen bits in a round robin fashion xored with the first 64-bit result element shifted right by sixty one bits in a round robin fashion xored with the first 64-bit result element shifted right by six bits; A fourth 64-bit result element, the fourth 64-bit result element being equal to the fourth 64-bit data element added to a value equal to the second 64-bit result element shifted right by nineteen bits in a round and the second 64-bit result element shifted right by sixty-one bits in a round and the second 64-bit result element shifted right by six bits in a round, and The result is stored in the destination.
20. 20. The non-transitory machine readable storage medium of claim 19, wherein the first 64-bit data element is to be stored in bits [63:0] of the first vector register, the second 64-bit data element is to be stored in bits [127:64] of the first vector register, the third 64-bit data element is to be stored in bits [191:128] of the first vector register, and the fourth 64-bit data element is to be stored in bits [255:192] of the first vector register, and wherein the first instruction specifies a YMM register.

Description

Apparatus, method, and system for hashing instructions The present application is filed on 3/2020 and 202010139487.7, entitled "apparatus, method, and System for hashing Instructions". Technical Field The present disclosure relates generally to electronics, and more particularly, embodiments of the present disclosure relate to processor circuits for hashing operations. Background A processor or set of processors execute instructions from an instruction set (e.g., an Instruction Set Architecture (ISA)). The instruction set is part of the computer architecture with respect to programming and generally includes native data types, instructions, register architecture, addressing modes, memory architecture, interrupt and exception handling, and external input and output (I/O). It should be noted that the term "instruction" may refer herein to a macro-instruction, e.g., an instruction provided to a processor for execution, or to a micro-instruction, e.g., an instruction generated by decoding a macro-instruction by decoding circuitry of the processor. Drawings The present disclosure is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements and in which: fig. 1 illustrates a hardware processor coupled to a memory according to an embodiment of the disclosure. Fig. 2 illustrates a hardware processor coupled to a store including one or more hash instructions, according to an embodiment of the present disclosure. Figure 3 illustrates a compression function of the SM3 hash standard according to an embodiment of the present disclosure. Figure 4A illustrates a pseudo code segment for performing hashing according to the SM3 hashing standard, according to an embodiment of the present disclosure. Figure 4B illustrates another pseudo code segment for performing hashing according to the SM3 hashing standard, according to an embodiment of the present disclosure. Figure 5 illustrates a method of processing a hash instruction according to the SM3 hash standard, according to an embodiment of the present disclosure. Fig. 6 illustrates a circuit including an execution circuit having a cyclic shift circuit and an SM3 hash wheel circuit, according to an embodiment of the present disclosure. Figure 7 illustrates a method of processing a pre-cyclic shift instruction according to the SM3 hash standard, according to an embodiment of the present disclosure. Fig. 8 illustrates a circuit including an execution circuit having a cyclic shift circuit according to an embodiment of the present disclosure. Figure 9 illustrates a method of processing a post-cyclic shift instruction according to the SM3 hash standard, according to an embodiment of the present disclosure. Fig. 10 illustrates a circuit including an execution circuit having a cyclic shift circuit according to an embodiment of the present disclosure. Figure 11 illustrates a method of processing an intermediate message instruction according to the SM3 hash standard, according to an embodiment of the present disclosure. Figure 12 illustrates a circuit including an execution circuit with an intermediate SM3 message calculation circuit, according to an embodiment of the present disclosure. Figure 13 illustrates an intermediate SM3 message calculation circuit according to an embodiment of the present disclosure. Figure 14 illustrates a method of processing a final message instruction according to the SM3 hash standard, according to an embodiment of the present disclosure. Figure 15 illustrates a circuit including an execution circuit with a final SM3 message calculation circuit, according to an embodiment of the present disclosure. Figure 16 illustrates a final SM3 message calculation circuit according to an embodiment of the present disclosure. Fig. 17 illustrates a SHA512 hash circuit in accordance with an embodiment of the present disclosure. Fig. 18 illustrates a method of processing a hash instruction according to the SHA512 hash standard, according to an embodiment of the present disclosure. Fig. 19 illustrates a circuit including an execution circuit with SHA512 hash wheel circuitry, according to an embodiment of the present disclosure. Fig. 20 illustrates a method of processing an intermediate message instruction according to the SHA512 hashing standard, in accordance with an embodiment of the present disclosure. Fig. 21 illustrates a circuit including an execution circuit with an intermediate SHA512 message calculation circuit, in accordance with an embodiment of the present disclosure. Fig. 22 illustrates a method of processing a final message instruction according to the SHA512 hashing standard, in accordance with an embodiment of the present disclosure. Fig. 23 illustrates a circuit including an execution circuit with a final SHA512 message calculation circuit, in accordance with an embodiment of the present disclosure. Fig. 24A is a block diagram illustrating a generic