CN-114550804-B - Error injection method using soft post-package repair (sPPR) technique and memory device and memory system employing the same

Abstract

The present disclosure relates to an error injection method using a soft post-package repair (sPPR) technique and a memory device and a memory system employing the same. Methods for operating a memory system are disclosed herein. In one embodiment, a method includes receiving first data to be written at a logical address of a memory array, storing the first data at a first physical address corresponding to the logical address, and remapping the logical address to a second physical address using, for example, a soft-packed repair operation. The method further includes receiving second data to be written at the logical address that is different from the first data, storing the second data at the second physical address, and remapping the logical address to the first physical address. In some embodiments, a method includes storing first and second ECC data corresponding to first and second data, respectively. The method further includes outputting the first data and/or the second ECC data in response to a read request corresponding to the logical address.

Inventors

• R. J. Rooney
• M. A. Blaise
• N. J. Coyle

Assignees

• 美光科技公司

Dates

Publication Date

20260512

Application Date

20211109

Priority Date

20211102

Claims (20)

1. 1. A method of operating a memory system, the method comprising: Receiving first data to be written at a logical address; storing the first data at a first physical address corresponding to the logical address; Remapping the logical address to a second physical address after storing the first data and before reading the first data; Receiving second data to be written at the logical address that is different from the first data; Storing the second data at the second physical address; Remapping the logical address to the first physical address after storing the second data, and After storing the second data and after remapping the logical address to the first physical address, the first data is output from the first physical address in response to a read request corresponding to the logical address.
2. 2. The method of claim 1, wherein the first data corresponds to the second data having one or more errors intentionally injected.
3. 3. The method of claim 2, wherein the one or more errors comprise bit insertion, bit deletion, or bit inversion.
4. 4. The method of claim 1, further comprising enabling a soft post-package repair sPPR function prior to receiving the first data.
5. 5. The method of claim 1, wherein remapping the logical address to the second physical address comprises performing a post-soft-package repair sPPR.
6. 6. The method of claim 1, wherein remapping the logical address to the first physical address comprises performing a post-soft-package repair sPPR.
7. 7. The method of claim 1, wherein the first physical address and the second physical address correspond to a first row and a second row of a memory array, respectively.
8. 8. The method of claim 1, further comprising outputting ECC data in addition to the first data in response to the read request corresponding to the logical address, wherein the ECC data corresponds to the second data.
9. 9. A memory system, comprising: a memory array comprising a plurality of rows, and Circuitry configured to: In response to a command to write first data at a logical address, writing the first data to a first physical address corresponding to the logical address; Remapping the logical address to a second physical address after writing the first data and before reading the first data; Writing second data different from the first data to the second physical address in response to a command to write the second data at the logical address; Remapping the logical address to the first physical address after writing the second data, and After writing the second data and after remapping the logical address to the first physical address, the first data is output from the first physical address in response to a read request corresponding to the logical address.
10. 10. The memory system of claim 9, wherein the first data corresponds to the second data having one or more errors intentionally injected.
11. 11. The memory system of claim 10, wherein the one or more errors comprise bit insertion, bit deletion, or bit inversion.
12. 12. The memory system of claim 10, wherein the circuitry is further configured to enable a soft post-package repair sPPR function prior to receiving the first data.
13. 13. The memory system of claim 10, wherein the circuitry is configured to remap the logical address to the second physical address by performing a post-soft-package repair sPPR.
14. 14. The memory system of claim 10, wherein the circuitry is configured to remap the logical address to the first physical address by performing a post-soft-package repair sPPR.
15. 15. The memory system of claim 10, wherein the first physical address and the second physical address correspond to a first row and a second row of a memory array, respectively.
16. 16. The memory system of claim 9, wherein the circuitry is further configured to output ECC data in addition to the first data in response to the read request corresponding to the logical address, wherein the ECC data corresponds to the second data.
17. 17. A method of operating a memory system including a first memory device and a second memory device, the method comprising: writing first user data to a first logical address of the first memory device, wherein the first logical address corresponds to a first physical address of the first memory device; Remapping the first logical address to a second physical address of the first memory device after writing the first user data and before reading the first user data; Calculating ECC data corresponding to the second user data; writing the second user data to the first logical address of the first memory device and writing the ECC data to a second logical address of the second memory device; remapping the first logical address to the first physical address of the first memory device after writing the second user data, and After writing the second user data and after remapping the first logical address to the first physical address of the first memory device and in response to a read request targeting the first logical address of the first memory device and the second logical address of the second memory device, the first user data is output from the first physical address of the first memory device and the ECC data is output from the second logical address of the second memory device.
18. 18. The method of claim 17, wherein the first physical address and the second physical address correspond to a first row and a second row of a memory array, respectively.
19. 19. The method of claim 17, wherein the first user data corresponds to the second user data having one or more errors intentionally injected.
20. 20. The method of claim 17, wherein remapping the first logical address to the second physical address comprises performing a post-soft-package repair sPPR.

Description

Error injection method using soft post-package repair (sPPR) technique and memory device and memory system employing the same Cross Reference to Related Applications The present application claims priority from U.S. provisional patent application No. 63/112,088, filed 11/10/2020, the disclosure of which is incorporated herein by reference in its entirety. Technical Field The present disclosure relates to memory systems, devices, and associated methods. In particular, the present disclosure relates to error injection methods using soft post-package repair (sPPR) techniques and memory devices and memory systems employing the methods. Background Memory devices are widely used to store information related to various electronic devices such as computers, wireless communication devices, cameras, digital displays, and the like. Memory devices are often provided as internal semiconductor integrated circuits and/or external removable devices in a computer or other electronic device. There are many different types of memory, including volatile and non-volatile memory. Volatile memories, including Static Random Access Memory (SRAM), dynamic Random Access Memory (DRAM), synchronous Dynamic Random Access Memory (SDRAM), and the like, may require an applied power to maintain their data. In contrast, nonvolatile memory can retain its stored data even when no external power is supplied. Nonvolatile memory may be used in a wide variety of technologies, including flash memory (e.g., NAND and NOR) Phase Change Memory (PCM), ferroelectric random access memory (FeRAM), resistive Random Access Memory (RRAM), and Magnetic Random Access Memory (MRAM), among others. Improving memory devices may generally include increasing memory cell density, increasing read/write speed or otherwise reducing operating latency, increasing reliability, increasing data retention, reducing power consumption or reducing manufacturing costs, among other metrics. Disclosure of Invention In one aspect, the present disclosure is directed to a method that includes receiving first data to be written at a logical address, storing the first data at a first physical address corresponding to the logical address, remapping the logical address to a second physical address, receiving second data different from the first data to be written at the logical address, storing the second data at the second physical address, remapping the logical address to the first physical address, and outputting the first data from the first physical address in response to a read request corresponding to the logical address. In another aspect, the present disclosure is directed to an apparatus comprising a memory array comprising a plurality of rows and circuitry configured to write first data to a first physical address corresponding to a logical address in response to a command to write the first data at the logical address, remap the logical address to a second physical address, write second data to the second physical address in response to a command to write second data different from the first data at the logical address, remap the logical address to the first physical address, and output the first data from the first physical address in response to a read request corresponding to the logical address. In yet another aspect, the present disclosure is directed to a method of operating a memory system including a first memory device and a second memory device, the method comprising writing first user data to a first logical address of the first memory device, wherein the first logical address corresponds to a first physical address of the first memory device, remapping the first logical address to a second physical address of the first memory device, calculating ECC data corresponding to second user data, writing the second user data to the first logical address of the first memory device and writing the ECC data to a second logical address of the second memory device, remapping the first logical address to the first physical address of the first memory device, outputting the first user data from the first physical address of the first memory device and outputting the second data from the second logical address of the second memory device in response to a read request targeting the first logical address of the first memory device and the second logical address of the second memory device. Drawings Many aspects of the disclosure can be better understood with reference to the following drawings. The components in the drawings are not necessarily to scale. Emphasis instead being placed upon clearly illustrating the principles of the present disclosure. The drawings should not be taken to limit the disclosure to the specific embodiments depicted, but are for explanation and understanding only. FIG. 1A is a block diagram schematically illustrating a memory system configured according to various embodiments of the present technology. FIG. 1B is a block diagram schematically illustrating a