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CN-114551764-B - Vertical transistor, display pixel, vertical light-emitting transistor, and display panel

CN114551764BCN 114551764 BCN114551764 BCN 114551764BCN-114551764-B

Abstract

The embodiment of the disclosure provides a vertical transistor, a display pixel, a vertical light-emitting transistor and a display panel, wherein the vertical transistor comprises a source electrode layer, a first active layer, a grid electrode layer, a second active layer and a drain electrode layer which are sequentially stacked in the vertical direction, the grid electrode layer comprises a first grid electrode structure and a second grid electrode structure, the first active layer and the second active layer form Schottky contact with the first grid electrode structure, the first grid electrode structure is located in a vertical stacking connection area, a first active overlapping area exists in the vertical direction with the source electrode layer, a second active overlapping area exists in the vertical direction with the grid electrode layer, the first grid electrode structure adopts sparse grid electrode materials or has a sparse hollow structure, the first active overlapping area is a projection overlapping part of two connection surfaces of the first active layer, the source electrode layer and the grid electrode layer, the second active overlapping area is a projection overlapping part of two connection surfaces of the second active layer, the drain electrode layer and the grid electrode layer, and the second grid electrode structure are located in a non-vertical stacking connection area.

Inventors

  • SONG ZUNQING

Assignees

  • 京东方科技集团股份有限公司

Dates

Publication Date
20260508
Application Date
20220225

Claims (10)

  1. 1. A vertical transistor is provided which has a high voltage and a high current, characterized in that it comprises at least: a source electrode layer, a grid electrode layer, a drain electrode layer, a first active layer and a second active layer; The source electrode layer, the first active layer, the gate electrode layer, the second active layer and the drain electrode layer are sequentially stacked in the vertical direction, the gate electrode layer comprises a first gate structure and a second gate structure, the first active layer and the second active layer form Schottky contact with the first gate structure, and the vertical direction is the direction vertical to the substrate; The first gate structure is located in a vertical stacking connection region, a first active overlapping region exists between the first gate structure and the source layer in the vertical direction, a second active overlapping region exists between the first gate structure and the gate layer in the vertical direction, the first gate structure is made of sparse gate material or has a sparse hollowed-out structure, the first active overlapping region is a projection overlapping part of two connection surfaces of the first active layer, the source layer and the gate layer, and the second active overlapping region is a projection overlapping part of two connection surfaces of the second active layer, the drain layer and the gate layer; the second gate structure is located in the non-vertical stacking connection region, connected to the first gate structure, and configured to receive a voltage signal.
  2. 2. The vertical transistor of claim 1, it is characterized in that the method is characterized in that, The second grid structure is made of a material processed in a metallization mode, is arranged in a self-alignment mode by taking the drain electrode layer as a mask, and is also connected with the second active layer.
  3. 3. The vertical transistor according to claim 1 or 2, wherein, The sparse gate material at least comprises one of a nanotube, a nanowire and graphene; the hollow pattern of the sparse hollow structure at least comprises one of a polygon, a circle and an ellipse.
  4. 4. A display pixel comprising at least: a source electrode layer, a grid electrode layer, a drain electrode layer, a first active layer and a second active layer; The source electrode layer, the first active layer, the gate electrode layer, the second active layer and the drain electrode layer are sequentially stacked in the vertical direction, the gate electrode layer comprises a first gate structure and a second gate structure, the first active layer and the second active layer form Schottky contact with the first gate structure, and the vertical direction is the direction vertical to the substrate; The first gate structure is located in a vertical stacking connection region, a first active overlapping region exists between the first gate structure and the source layer in the vertical direction, a second active overlapping region exists between the first gate structure and the gate layer in the vertical direction, the first gate structure is made of sparse gate material or has a sparse hollowed-out structure, the first active overlapping region is a projection overlapping part of two connection surfaces of the first active layer, the source layer and the gate layer, and the second active overlapping region is a projection overlapping part of two connection surfaces of the second active layer, the drain layer and the gate layer; The second grid structure is positioned in the non-vertical stacking connection area, connected with the first grid structure and used for receiving voltage signals; the drain electrode layer is provided with a light-emitting layer, or the vertical stacking connection area of the drain electrode layer is connected with an anode layer, and the anode layer is provided with a light-emitting layer.
  5. 5. The display pixel of claim 4, wherein, The second grid structure is made of a material processed in a metallization mode, is arranged in a self-alignment mode by taking the drain electrode layer as a mask, and is also connected with the second active layer.
  6. 6. The display pixel of claim 4 or 5, wherein, The sparse gate material at least comprises one of a nanotube, a nanowire and graphene; the hollow pattern of the sparse hollow structure at least comprises one of a polygon, a circle and an ellipse.
  7. 7. A vertical light emitting transistor, comprising at least: a source electrode layer, a grid electrode layer, a drain electrode layer, a first active layer and a second active layer; The source electrode layer, the first active layer, the gate electrode layer, the second active layer and the drain electrode layer are sequentially stacked in the vertical direction, the gate electrode layer comprises a first gate structure and a second gate structure, the first active layer and the second active layer form Schottky contact with the first gate structure, and the vertical direction is the direction vertical to the substrate; The first gate structure is located in a vertical stacking connection region, a first active overlapping region exists between the first gate structure and the source layer in the vertical direction, a second active overlapping region exists between the first gate structure and the gate layer in the vertical direction, the first gate structure is made of sparse gate material or has a sparse hollowed-out structure, the first active overlapping region is a projection overlapping part of two connection surfaces of the first active layer, the source layer and the gate layer, and the second active overlapping region is a projection overlapping part of two connection surfaces of the second active layer, the drain layer and the gate layer; The second grid structure is positioned in the non-vertical stacking connection area, connected with the first grid structure and used for receiving voltage signals; Wherein the drain layer, the first active layer, and the second active layer are made of an organic semiconductor material, so that the drain layer emits light by current excitation from the source layer to the second active layer.
  8. 8. The vertical luminescence transistor according to claim 7, The second grid structure is made of a material processed in a metallization mode, is arranged in a self-alignment mode by taking the drain electrode layer as a mask, and is also connected with the second active layer.
  9. 9. The vertical luminescence transistor according to claim 7 or 8, wherein, The sparse gate material at least comprises one of a nanotube, a nanowire and graphene; the hollow pattern of the sparse hollow structure at least comprises one of a polygon, a circle and an ellipse.
  10. 10. A display panel, comprising at least: A plurality of display pixels as claimed in any one of claims 4 to 6, and/or, A plurality of vertical light emitting transistors according to any one of claims 7 to 9.

Description

Vertical transistor, display pixel, vertical light-emitting transistor, and display panel Technical Field The present disclosure relates to the field of display and control, and in particular, to a vertical transistor, a display pixel, a vertical light emitting transistor, and a display panel. Background A Gate-Source-drain vertically distributed Organic FIELD EFFECT Transistor (VOFET) structure is formed by superposing an active layer and a drain electrode on a plate capacitor unit, so that the distance between the Source and the drain (the deposition thickness of the active layer, namely the channel length) can be reduced, the area of a conducting channel between the Source and the drain can be increased, and the problems of higher working voltage and smaller working current of the Organic field effect Transistor caused by overlarge Organic semiconductor resistance can be solved. However, the channel depth is controlled by the gate, which can usually only stay in a few nanometers, and cannot be adjusted more under the same voltage, and cannot further reduce the operating voltage under the same operating current, so that the device performance is low. Disclosure of Invention In view of the above, the embodiments of the present disclosure provide a vertical transistor, a display pixel, a vertical light emitting transistor, and a display panel, which are used for solving the problems in the prior art that the existing transistor cannot perform larger adjustment on the operating current under the same voltage, cannot further reduce the operating voltage under the same operating current, and has lower device performance. In one aspect, the embodiment of the disclosure provides a vertical transistor, which at least comprises a source electrode layer, a gate electrode layer, a drain electrode layer, a first active layer and a second active layer, wherein the source electrode layer, the first active layer, the gate electrode layer, the second active layer and the drain electrode layer are sequentially stacked in the vertical direction, the gate electrode layer comprises a first gate electrode structure and a second gate electrode structure, the first active layer and the second active layer form Schottky contact with the first gate electrode structure, the vertical direction is the direction vertical to a substrate, the first gate electrode structure is located in a vertical stacking connection region, a first active overlapping region is located in the vertical direction with the source electrode layer, a second active overlapping region is located in the vertical direction with the gate electrode layer, the first gate electrode structure adopts a sparse gate electrode material or has a sparse hollow structure, the first active region is a projection area where the first active layer overlaps the source electrode layer and the gate electrode layer, the second active layer overlaps with the first gate electrode structure, the second active layer is located in a projection area where the second active layer overlaps with the second gate electrode structure, and the second active layer is located in the vertical stacking connection region. In some embodiments, the second gate structure is formed by using a material processed in a metallization manner, and is disposed in a self-aligned manner by using the drain layer as a mask, and the second gate structure is further connected to the second active layer. In some embodiments, the sparse gate material comprises at least one of a nanotube, a nanowire and graphene, and the hollowed pattern of the sparse hollowed structure comprises at least one of a polygon, a circle and an ellipse. On the other hand, the embodiment of the disclosure provides a display pixel, which at least comprises a source electrode layer, a grid electrode layer, a drain electrode layer, a first active layer and a second active layer, wherein the source electrode layer, the first active layer, the grid electrode layer, the second active layer and the drain electrode layer are sequentially stacked in the vertical direction, the grid electrode layer comprises a first grid electrode structure and a second grid electrode structure, the first active layer and the second active layer form Schottky contact with the first grid electrode structure, the vertical direction is the direction perpendicular to a substrate, the first grid electrode structure is located in a vertical stacking connection region, a first active overlapping region is located in the vertical direction with the source electrode layer, a second active overlapping region is located in the vertical direction with the grid electrode layer, the first grid electrode structure adopts sparse grid electrode materials or has sparse hollow structures, the first active overlapping region is a projection region of two connection surfaces of the first active layer and the grid electrode layer, the second active layer is located in a vertical stacking