CN-114582911-B - Photoelectric integrated device and preparation method thereof

CN114582911BCN 114582911 BCN114582911 BCN 114582911BCN-114582911-B

Abstract

The invention discloses a photoelectric integrated device and a manufacturing method thereof, wherein the photoelectric integrated device comprises a plurality of basic units which are orderly arranged, the basic units comprise a multi-quantum well MicroLED and a vertical structure GaN MOSFET, a bonding medium layer is arranged on the top layer of a sapphire substrate, the bottom layer of the sapphire substrate is a light-emitting surface of the device, a multi-quantum well Micro LED is arranged on the top layer of the bonding medium layer, the vertical structure GaN MOSFET is arranged above the multi-quantum well Micro LED, a drain region of the vertical structure GaN MOSFET and an N region of the multi-quantum well Micro LED are connected in series through a shared diode N-GaN structure layer, the light-emitting device and a driving electronic device are manufactured on the same chip, not only can batch manufacturing be realized by utilizing the existing GaN process platform, but also have the remarkable advantages of small volume, high speed and high reliability, and the GaN MOSFET adopts a novel vertical structure design, so that the channel length of the driving transistor can be greatly shortened, and has important significance in improving the performance and the integration degree of the integrated device.

Inventors

YAN JIABIN
SHI FAN
YANG LINGYUN
WU JIE
DAI YELING

Assignees

南京邮电大学

Dates

Publication Date: 20260505
Application Date: 20220127

Claims (7)

1. An optoelectronic integrated device, comprising: A plurality of sequentially arranged basic cells including a multi-quantum well MicroLED and a vertical-structure GaN MOSFET; The device comprises a sapphire substrate, wherein a bonding medium layer is arranged on the top layer of the sapphire substrate, and the bottom layer of the sapphire substrate is a light-emitting surface of the device; The vertical structure GaN MOSFET is arranged above the multi-quantum well Micro LED, and the drain region of the vertical structure GaN MOSFET is connected in series with the N region of the multi-quantum well Micro LED through a shared diode N-GaN structure layer; The vertical-structure GaN MOSFET comprises a diode N-GaN structure layer, a transistor P-GaN channel layer, a transistor source region N-GaN structure layer and a transistor source metal layer from bottom to top in sequence; The diode comprises a diode N-GaN structure layer, a transistor P-GaN channel layer and a transistor source region N-GaN structure layer, wherein a transistor gate metal layer is covered on the side wall of the diode N-GaN structure layer, and a gate dielectric layer is arranged on the outer side of the transistor gate metal layer in an isolated mode.
2. The optoelectronic integrated device according to claim 1, wherein the active region of the multi-quantum well Micro LED comprises, from bottom to top, a diode P-GaN structure layer, a diode multi-quantum well structure layer and a diode N-GaN structure layer, wherein the diode anode is arranged around the basic unit and is in direct contact with the diode P-GaN structure layer, and the diode anode is in grid distribution.
3. The optoelectronic integrated device of claim 1, wherein sidewall tilt angles of the transistor P-GaN channel layer and the transistor source region N-GaN structure layer are less than 90 degrees.
4. A method of manufacturing an optoelectronic integrated device using any one of claims 1-3, the method comprising: Firstly, coating a layer of photoresist on the sapphire on the back of an epitaxial wafer of an integrated chip, and photoetching to form a patterned structure on a light-emitting surface; coating a layer of photoresist on the epitaxial wafer of the integrated chip, forming a side wall inclination angle by using a photoresist reflow method, exposing a region to be etched on the platform after photoetching, and etching until the diode N-GaN structural layer stops to form the side wall of the transistor grid electrode; Thirdly, coating a layer of photoresist and photoetching to expose a region to be etched, and etching until the diode P-GaN structure layer is stopped to form a light-emitting platform region; annealing the etched integrated chip epitaxial wafer in nitrogen to remove hydrogen element in the transistor P-GaN channel layer and activate the P-GaN; Step five, growing a gate dielectric layer on the epitaxial wafer of the integrated chip, and etching and forming the integrated chip after photoetching; step six, respectively forming a diode anode, a transistor grid electrode metal layer and a metal tube source electrode metal layer by adopting a stripping method; seventh, using the isolation medium as an electrical isolation layer between different interconnection metal layers, growing a plurality of interconnection metal layers, and respectively connecting the electrodes of the same type of different basic units into a unified whole to form the whole photoelectric integrated device; the preparation method of the integrated chip epitaxial wafer comprises the following steps: The method comprises the steps that a multi-quantum well LED epitaxial wafer is selected as an LED wafer, and epitaxial materials of the multi-quantum well LED epitaxial wafer sequentially comprise a first sapphire, a buffer layer, an unintentionally doped GaN layer, an N-GaN layer, a multi-quantum well and a P-GaN layer from bottom to top, wherein a second sapphire is arranged on the P-GaN layer and is used as a transfer substrate; secondly, a transparent bonding medium layer grows above the second sapphire or P-GaN layer, and bonding of the LED wafer and the transfer substrate is realized in the pressure, temperature and gas environment; Removing the first sapphire of the bonding sheet, and removing the buffer layer and the unintentionally doped GaN layer of the bonding sheet to expose the N-GaN layer; and fourthly, sequentially extending a P-GaN epitaxial layer and an N-GaN epitaxial layer above the N-GaN layer to obtain the integrated chip epitaxial wafer.
5. The method for manufacturing an optoelectronic integrated device according to claim 4, wherein the integrated chip epitaxial wafer is grown with a gate dielectric layer by using a pressure chemical vapor deposition method or atomic layer deposition method.
6. The method of claim 4, wherein the annealing is performed at a temperature of 700 degrees celsius for 30 minutes.
7. The method of claim 4, wherein the bonding dielectric layer is located between the LED wafer and the transfer substrate.

Description

Photoelectric integrated device and preparation method thereof Technical Field The invention relates to a photoelectric integrated device and a preparation method thereof, belonging to the technical field of integrated photoelectrons. Background The band gap of III-V semiconductor GaN and its alloys covers the spectrum from infrared to visible, and has achieved great success in solid state lighting, display, high density storage, and underwater communications. Meanwhile, the GaN-based transistor technology is paid attention to in the industry in recent years, is rapidly developed, and has an attractive application prospect in the aspects of high-power and high-frequency devices and the like. At present, gaN is studied independently of electronic technology, but in practical application, the electronic technology is inseparable and interdependent, for example, a GaN Light Emitting Diode (LED) must be driven by an electronic transistor circuit, and the existing electronic transistor circuit is manufactured separately based on a silicon-based platform and electrically connected to a photoelectric component in an off-chip package mode. The GaN photoelectric device and the electronic device are integrated on the same platform to form a so-called photoelectric monolithic integrated circuit, and compared with the traditional off-chip packaging interconnection, the GaN photoelectric device and the electronic device have the remarkable advantages of small size, light weight, low cost, high speed, less parasitics, multiple functions, high reliability and the like. Disclosure of Invention The invention aims to provide a photoelectric integrated device and a preparation method thereof, which are used for solving the defect that the existing electronic transistor circuits are manufactured independently based on a silicon-based platform and have large volume. An optoelectronic integrated device comprising: a plurality of basic units which are orderly arranged, wherein the basic units comprise a multi-quantum well Micro LED and a GaN MOSFET with a vertical structure; The device comprises a sapphire substrate, wherein a bonding medium layer is arranged on the top layer of the sapphire substrate, and the bottom layer of the sapphire substrate is a light-emitting surface of the device; the GaN MOSFET with the vertical structure is arranged above the Micro LED with the multiple quantum wells, and the drain region of the GaN MOSFET with the vertical structure is connected with the N region of the Micro LED with the multiple quantum wells in series through the N-GaN structure layer of the shared diode. Further, the active area of the multi-quantum well Micro LED sequentially comprises a diode P-GaN structural layer, a diode multi-quantum well structural layer and a diode N-GaN structural layer from bottom to top, diode anodes are arranged on the periphery of the basic unit and are in direct contact with the diode P-GaN structural layer, and the diode anodes are distributed in a grid shape. Further, the vertical structure GaN MOSFET comprises a diode N-GaN structure layer, a transistor P-GaN channel layer, a transistor source region N-GaN structure layer and a transistor source metal layer from bottom to top in sequence; The diode comprises a diode N-GaN structure layer, a transistor P-GaN channel layer and a transistor source region N-GaN structure layer, wherein a transistor gate metal layer is covered on the side wall of the diode N-GaN structure layer, and a gate dielectric layer is arranged on the outer side of the transistor gate metal layer in an isolated mode. Further, the inclination angles of the side walls of the transistor P-GaN channel layer and the transistor source region N-GaN structure layer are smaller than the degree. A method for manufacturing an optoelectronic integrated device using the above, the method comprising: Firstly, coating a layer of photoresist on the sapphire on the back of an epitaxial wafer of an integrated chip, and photoetching to form a patterned structure on a light-emitting surface; coating a layer of photoresist on the epitaxial wafer of the integrated chip, forming a side wall inclination angle by using a photoresist reflow method, exposing a region to be etched on the platform after photoetching, and etching until the diode N-GaN structural layer stops to form the side wall of the transistor grid electrode; Thirdly, coating a layer of photoresist and photoetching to expose a region to be etched, and etching until the diode P-GaN structure layer is stopped to form a light-emitting platform region; annealing the etched integrated chip epitaxial wafer in nitrogen to remove hydrogen element in the transistor P-GaN channel layer and activate the P-GaN; Step five, growing a gate dielectric layer on the epitaxial wafer of the integrated chip, and etching and forming the integrated chip after photoetching; step six, respectively forming a diode anode, a transistor grid electrode metal layer an