CN-114597209-B - Transistor gate structure and forming method thereof

Abstract

The application relates to a transistor gate structure and a method of forming the same. In one embodiment, a device includes a channel region, a gate dielectric layer over the channel region, a first work function tuning layer over the gate dielectric layer, the first work function tuning layer comprising a p-type work function metal, a barrier layer over the first work function tuning layer, a second work function tuning layer over the barrier layer, the second work function tuning layer comprising an n-type work function metal, the n-type work function metal being different from the p-type work function metal, and a filler layer over the second work function tuning layer.

Inventors

• LI XINYI
• HONG ZHENGLONG
• XU ZHIAN

Assignees

• 台湾积体电路制造股份有限公司

Dates

Publication Date

20260512

Application Date

20210525

Priority Date

20210407

Claims (20)

1. 1. A transistor gate structure comprising: A nanostructure; a gate dielectric layer on the nanostructure; A first work function tuning layer on the gate dielectric layer, the first work function tuning layer comprising a p-type work function metal, the first work function tuning layer and the gate dielectric layer completely filling a region between the nanostructures; a barrier layer on the first work function tuning layer; A second work function tuning layer on the barrier layer, the second work function tuning layer comprising an n-type work function metal, the n-type work function metal being different from the p-type work function metal, and And a filling layer positioned on the second work function tuning layer.
2. 2. The transistor gate structure of claim 1, wherein the n-type workfunction metal comprises a metal element and the barrier layer is a single continuous layer of barrier material having a lower portion proximate the first workfunction tuning layer and having an upper portion proximate the second workfunction tuning layer, the upper portion of the barrier layer comprising a concentration of a residue of the metal element that is greater than a concentration of a residue of the metal element that is comprised by the lower portion of the barrier layer.
3. 3. The transistor gate structure of claim 1, wherein the n-type work function metal comprises a metal element and the barrier layer comprises: A first layer; a second layer on the first layer, the second layer containing a residue of the metal element at a concentration greater than that of the first layer, and An oxide layer between the first layer and the second layer, the oxide layer being thinner than the first layer and the second layer.
4. 4. The transistor gate structure of claim 3, wherein the first layer comprises a first barrier material, the oxide layer comprises an oxide of the first barrier material, and the second layer comprises a second barrier material, the second barrier material being different from the first barrier material.
5. 5. The transistor gate structure of claim 3, wherein the first layer comprises a barrier material, the oxide layer comprises an oxide of the barrier material, and the second layer comprises the barrier material.
6. 6. The transistor gate structure of claim 1, wherein the barrier layer comprises amorphous silicon.
7. 7. The transistor gate structure of claim 1, wherein the barrier layer comprises fluorine-free tungsten.
8. 8. The transistor gate structure of claim 1, wherein the barrier layer has a thickness in the range of 7 a to 40 a.
9. 9. A transistor gate structure comprising: a first transistor, the first transistor comprising: A first channel region comprising nanostructures; a first gate dielectric layer on the nanostructure; A p-type work function tuning layer on the first gate dielectric layer, the p-type work function tuning layer and the first gate dielectric layer completely filling the region between the nanostructures; A blocking layer on the p-type work function tuning layer; A first n-type work function tuning layer on the barrier layer, the first n-type work function tuning layer comprising a metal, the upper portion of the barrier layer comprising a greater concentration of residues of the metal than the lower portion of the barrier layer, the upper portion of the barrier layer being adjacent the first n-type work function tuning layer, the lower portion of the barrier layer being adjacent the p-type work function tuning layer, and A first filling layer on the first n-type work function tuning layer, and A second transistor, the second transistor comprising: A second channel region comprising nanostructures; a second gate dielectric layer on the nanostructure; A second n-type work function tuning layer on the second gate dielectric layer, the second n-type work function tuning layer comprising the metal, and And a second filling layer positioned on the second n-type work function tuning layer.
10. 10. The transistor gate structure of claim 9, wherein the barrier layer comprises a single continuous layer of barrier material between the p-type work function tuning layer and the first n-type work function tuning layer.
11. 11. The transistor gate structure of claim 9, wherein the barrier layer comprises a multilayer of barrier material between the p-type work function tuning layer and the first n-type work function tuning layer.
12. 12. The transistor gate structure of claim 9, wherein the metal is aluminum.
13. 13. A method for forming a transistor gate structure, comprising: Depositing a gate dielectric layer having a first portion deposited over the nanostructures of the first channel region and a second portion deposited over the nanostructures of the second channel region; depositing a first p-type work function tuning layer on the first portion of the gate dielectric layer, wherein the first p-type work function tuning layer and the first portion of the gate dielectric layer completely fill a region between nanostructures of the first channel region; Depositing a barrier layer on the first p-type work function tuning layer, and A second n-type work function tuning layer is deposited over the barrier layer and over the second portion of the gate dielectric layer, the barrier layer inhibiting modification of a first p-type work function of the first p-type work function tuning layer during deposition of the second n-type work function tuning layer.
14. 14. The method of claim 13, wherein depositing the barrier layer comprises depositing amorphous silicon by a CVD process performed using silane, the CVD process performed at a temperature of 275 ℃ to 500 ℃, the CVD process performed at a pressure of 3 torr to 45 torr, the barrier layer deposited to have a thickness of 7 a to 40 a.
15. 15. The method of claim 13, wherein depositing the barrier layer comprises depositing fluorine-free tungsten by an ALD process performed using tungsten chloride (V) and hydrogen, the ALD process performed at a temperature of 250 ℃ to 550 ℃, the ALD process performed at a pressure of 0.1 torr to 60 torr, the barrier layer deposited to have a thickness of 7a to 40 a.
16. 16. The method of claim 13, wherein depositing the second n-type work function tuning layer comprises depositing a metal, the barrier layer inhibiting diffusion of the metal into the first p-type work function tuning layer during deposition of the second n-type work function tuning layer.
17. 17. The method of claim 13, wherein forming the first p-type work function tuning layer comprises depositing the first p-type work function tuning layer on the first portion and the second portion of the gate dielectric layer, and wherein forming the barrier layer comprises: depositing the barrier layer on the first p-type work function tuning layer, and Portions of the barrier layer and the first p-type work function tuning layer are removed to expose the second portion of the gate dielectric layer.
18. 18. The method of claim 17, wherein depositing the barrier layer comprises depositing a single continuous layer of barrier material.
19. 19. The method of claim 17, wherein depositing the barrier layer comprises: Depositing a first barrier material; Oxidizing an upper portion of the first barrier material, and A second barrier material is deposited over the first barrier material after oxidizing an upper portion of the first barrier material.
20. 20. The method of claim 17, wherein depositing the barrier layer comprises: Depositing a barrier material; oxidizing an upper portion of the barrier material, and After oxidizing the upper portion of the barrier material, more of the barrier material is deposited.

Description

Transistor gate structure and forming method thereof Technical Field The present application relates to the field of semiconductors, and more particularly to transistor gate structures and methods of forming the same. Background Semiconductor devices are used in a variety of electronic applications, such as personal computers, cellular telephones, digital cameras, and other electronic devices. Semiconductor devices are typically fabricated by sequentially depositing materials of insulating or dielectric layers, conductive layers, and semiconductor layers on a semiconductor substrate, and patterning the various material layers using photolithography to form circuit components and elements thereon. The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continually reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size decreases, additional problems to be solved arise. Disclosure of Invention According to one aspect of the present disclosure, a transistor gate structure is provided that includes a channel region, a gate dielectric layer over the channel region, a first work function tuning layer over the gate dielectric layer, the first work function tuning layer comprising a p-type work function metal, a barrier layer over the first work function tuning layer, a second work function tuning layer over the barrier layer, the second work function tuning layer comprising an n-type work function metal, the n-type work function metal being different from the p-type work function metal, and a filler layer over the second work function tuning layer. According to another aspect of the present disclosure, a transistor gate structure is provided that includes a first transistor including a first channel region, a first gate dielectric layer on the first channel region, a p-type work function tuning layer on the first gate dielectric layer, a barrier layer on the p-type work function tuning layer, a first n-type work function tuning layer on the barrier layer, the first n-type work function tuning layer including a metal having a concentration of a residue of the metal included in an upper portion of the barrier layer that is greater than a concentration of a residue of the metal included in a lower portion of the barrier layer, the upper portion of the barrier layer being adjacent to the first n-type work function tuning layer, the lower portion of the barrier layer being adjacent to the p-type work function tuning layer, and a first fill layer on the first n-type work function tuning layer. The transistor gate structure further includes a second transistor including a second channel region, a second gate dielectric layer on the second channel region, a second n-type work function tuning layer on the second gate dielectric layer, the second n-type work function tuning layer including the metal, and a second fill layer on the second n-type work function tuning layer. According to yet another aspect of the present disclosure, a method for forming a transistor gate structure is provided, the method comprising depositing a gate dielectric layer having a first portion and a second portion, the first portion being deposited on a first channel region, the second portion being deposited on a second channel region, forming a first work function tuning layer on the first portion of the gate dielectric layer, forming a barrier layer on the first work function tuning layer, and depositing a second work function tuning layer on the barrier layer and on the second portion of the gate dielectric layer, the barrier layer inhibiting modification of a first work function of the first work function tuning layer during deposition of the second work function tuning layer. Drawings Aspects of the disclosure may be best understood from the following detailed description when read in connection with the accompanying drawings. It should be noted that the various features are not drawn to scale according to standard practices in the industry. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. Fig. 1 illustrates an example of a nanostructured field effect transistor (nanostructured FET) in a three-dimensional view according to some embodiments. Fig. 2, 3, 4, 5, 6, 7A, 7B, 8A, 8B, 9A, 9B, 9C, 9D, 10A, 10B, 11A, 11B, 12A, 12B, 13A, 13B, 14A, 14B, 15A, 15B, 16A, 16B, 17A, 17B, 18A, 18B, 19A, 19B, 20A, 20B, 21A, 21B, 22A, and 22B are views of intermediate stages of fabricating a nanostructure FET according to some embodiments. Fig. 23A and 23B are diagrams of nanostructure FETs according to some other embodiments. Detailed Description The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and ar