CN-114613409-B - Memory device including support structure

Abstract

The application relates to a memory device including a support structure. Some embodiments include apparatus and methods of forming the apparatus. One of the apparatus includes a respective memory cell level and a control gate, the levels overlying one another above a substrate, the control gate including a control gate nearest the substrate, the control gate including a respective portion forming a stepped structure, a conductive contact in contact with the control gate at a location of the stepped structure, the conductive contact including a conductive contact in contact with the control gate, a dielectric structure on a sidewall of the control gate, and a support structure adjacent the conductive contact and having a length extending vertically from the substrate, the support structure including a support structure nearest the conductive contact, the support structure being located a distance from an edge of the dielectric structure, wherein a ratio of a width of the support structure to the distance is in a range from 1.6 to 2.0.

Inventors

• WANG ZHEWEI
• L Ziyan
• YU SHUTING
• FU QITAO

Assignees

• 美光科技公司
• 美光科技公司

Dates

Publication Date

20260421

Application Date

20211202

Priority Date

20201203

Claims (20)

1. 1. A memory apparatus, comprising: A substrate; A deck, the deck overlying one another above the substrate, the deck including respective memory cells and a plurality of control gates for the memory cells, the plurality of control gates including a first control gate closest to the substrate and no other control gates, the plurality of control gates including respective portions that together form a stair-step structure; a conductive contact in contact with the plurality of control gates at a location of the stair-step structure, the conductive contact having different lengths extending vertically from the substrate, the conductive contact including a conductive contact in contact with the first control gate; a dielectric structure adjacent sidewalls of the plurality of control gates of the deck, and A plurality of support structures adjacent to the conductive contacts and electrically separated from the plurality of control gates and the conductive contacts, the plurality of support structures having a length extending vertically from the substrate and extending through at least a portion of the plurality of control gates, the plurality of support structures including a first support structure closest to the conductive contacts and not other support structures, the first support structure being located at a distance from an edge of the dielectric structure, wherein a ratio of a width of the first support structure to the distance is in a range from 1.6 to 2.0.
2. 2. The memory device of claim 1, wherein the first support structure has a width in a range from 345 nm to 375 nm.
3. 3. The memory device of claim 1, wherein the distance has a range from 190 nanometers to 203 nanometers.
4. 4. The memory device of claim 1, wherein each of the plurality of control gates has a thickness in a range from 30 nanometers to 35 nanometers.
5. 5. The memory device of claim 4, further comprising a level of dielectric material interleaved with the plurality of control gates, wherein a thickness of each of the layers of dielectric material is in a range from 22 nanometers to 27 nanometers.
6. 6. The memory device of claim 1, wherein the sidewall of the plurality of control gates is a first sidewall, the dielectric structure is a first dielectric structure, the distance is a first distance, and the memory device further comprises: a second dielectric structure on a second sidewall opposite to the first sidewall of the plurality of control gates, and The plurality of support structures includes a second support structure adjacent the first support structure and the conductive contact, the second support structure located a second distance from an edge of the second dielectric structure, wherein a ratio of a width of the second support structure to the second distance is in a range from 1.6 to 2.0.
7. 7. A memory apparatus, comprising: A substrate; A deck, the deck overlying one another above the substrate, the deck including respective memory cells and a plurality of control gates for the memory cells, the plurality of control gates including a first control gate closest to the substrate and no other control gates, the plurality of control gates including respective portions that together form a stair-step structure; a conductive contact in contact with the plurality of control gates at a location of the stair-step structure, the conductive contact having a different length extending vertically from the substrate, the conductive contact including a conductive contact in contact with the first control gate, and A plurality of support structures adjacent to the conductive contacts and electrically separated from the plurality of control gates and the conductive contacts, the plurality of support structures having a length extending vertically from the substrate and extending through at least a portion of the plurality of control gates, the plurality of support structures including a first support structure closest to the conductive contacts and no other support structures, wherein the first support structure has a width of at least 345 nanometers.
8. 8. The memory device of claim 7, wherein the width of the first support structure has a range from 345 nanometers to 375 nanometers.
9. 9. The memory device of claim 7, wherein the lengths of the plurality of support structures are the same.
10. 10. The memory device of claim 7, wherein a width of a second support structure of the plurality of support structures is different than the width of the first support structure.
11. 11. The memory device of claim 7, wherein each of the plurality of control gates has a thickness in a range from 30 nanometers to 35 nanometers.
12. 12. A memory apparatus, comprising: A substrate; A deck, the deck overlying one another above the substrate, the deck including respective memory cells and a plurality of control gates for the memory cells, the plurality of control gates including a first control gate closest to the substrate and no other control gates, the plurality of control gates including respective portions that together form a stair-step structure; a conductive contact in contact with the plurality of control gates at a location of the stair-step structure, the conductive contact having different lengths extending vertically from the substrate, the conductive contact including a conductive contact in contact with the first control gate; A plurality of support structures adjacent to the conductive contacts and electrically separated from the plurality of control gates and the conductive contacts, the plurality of support structures having a length extending vertically from the substrate and extending through at least a portion of the plurality of control gates, the plurality of support structures including a first support structure closest to the conductive contacts and not other support structures, and A dielectric structure adjacent sidewalls of the plurality of control gates, wherein a distance between an edge of the dielectric structure and an edge of the first support structure is less than 215 nanometers.
13. 13. The memory device of claim 12, wherein the distance is greater than 190 nanometers.
14. 14. The memory device of claim 12, wherein the first support structure has a width in a range from 345 nm to 375 nm.
15. 15. The memory device of claim 12, wherein the first support structure has a first width and a second support structure of the plurality of support structures has a second width that is greater than the first width.
16. 16. The memory device of claim 12, wherein each of the plurality of control gates has a thickness in a range from 30 nanometers to 35 nanometers.
17. 17. The memory device of claim 12, wherein the sidewall of the plurality of control gates is a first sidewall, the dielectric structure is a first dielectric structure, and the memory device further comprises: a second dielectric structure on a second sidewall opposite to the first sidewall of the plurality of control gates, and The plurality of support structures includes a second support structure adjacent the first support structure and the conductive contact, wherein a distance between an edge of the second dielectric structure and an edge of the second support structure is less than 215 nanometers.
18. 18. The memory device of claim 17, wherein the edge of the first support structure is a first edge, the first support structure includes a second edge closest to the second support structure, and a distance between the second edge of the first dielectric structure and an edge of the second dielectric structure is less than 214 nanometers.
19. 19. A method of forming a memory apparatus, comprising: Forming a stair-step structure over a substrate of the memory device, the stair-step structure including a first stair-step structure and a second stair-step structure, the first stair-step structure being closest to the substrate relative to the second stair-step structure; Forming conductive contacts in contact with respective ones of the levels of conductive material of the stair-step structure, the conductive contacts having different lengths extending vertically from the substrate, the conductive contacts including conductive contacts in contact with ones of the levels of conductive material, and A plurality of support structures are formed adjacent to and electrically separate from the conductive contact and the conductive material level, the plurality of support structures having a length extending vertically from the substrate and extending through at least a portion of the conductive material level, the plurality of support structures including a first support structure closest to the conductive contact and no other support structures, wherein the first support structure has a width of at least 345 nanometers.
20. 20. The method as recited in claim 19, further comprising: a dielectric structure is formed adjacent to sidewalls of the conductive material level, the dielectric structure including a slit and a dielectric material filled in the slit, wherein a distance between an edge of the dielectric structure and an edge of the first support structure is less than 215 nanometers.

Description

Memory device including support structure Technical Field Embodiments described herein relate to memory devices including support structures at stepped regions of the memory devices. Background The dimensions of the structures of the components in a memory device (e.g., a flash memory device) are relatively small (e.g., nano-sized). At a certain size, some structures of the memory device may collapse during fabrication of the memory device. Some conventional techniques use an additional chemical treatment step to prevent this collapse. However, additional steps may increase the cost of manufacturing the memory device. Disclosure of Invention One aspect of the disclosure provides an apparatus comprising a substrate, a layer comprising respective memory cells and control gates for the memory cells, the control gates comprising control gates closest to the substrate and not other control gates, the control gates comprising respective portions that together form a stepped structure, conductive contacts in contact with the control gates at locations of the stepped structure, the conductive contacts having different lengths extending vertically from the substrate, the conductive contacts comprising conductive contacts in contact with a first control gate, a dielectric structure adjacent a sidewall of the control gates of the layer, and a support structure adjacent the conductive contacts and electrically separated from the control gates and the conductive contacts, the support structure having a length extending vertically from the substrate and through at least a portion of the control gates, the support structure comprising a support structure closest to the conductive contacts and not other support structure, the support structure being located at a distance from the edge of the support structure at a ratio of 1.0 to the width. Another aspect of the disclosure provides an apparatus comprising a substrate, a deck overlying one another above the substrate, the deck including respective memory cells and control gates for the memory cells, the control gates including control gates closest to the substrate but not other control gates, the control gates including respective portions that together form a stepped structure, conductive contacts in contact with the control gates at locations of the stepped structure, the conductive contacts having different lengths extending vertically from the substrate, the conductive contacts including conductive contacts in contact with a first control gate, and a support structure adjacent to and electrically separated from the control gates and the conductive contacts, the support structure having a length extending vertically from the substrate and through at least a portion of the control gates, the support structure including support structures closest to the conductive contacts but not other support structures, wherein the support structure has a width of at least 345 nanometers. Another aspect of the disclosure provides an apparatus comprising a substrate, a layer comprising respective memory cells and control gates for the memory cells stacked one above the substrate, the control gates comprising control gates closest to the substrate and not other control gates, the control gates comprising respective portions that together form a stepped structure, conductive contacts in contact with the control gates at locations of the stepped structure, the conductive contacts having different lengths extending vertically from the substrate, the conductive contacts comprising conductive contacts in contact with the control gates, a support structure adjacent to and electrically separated from the control gates and the conductive contacts, the support structure having a length extending vertically from the substrate and through at least a portion of the control gates, the support structure comprising support structures closest to the conductive contacts and not other support structures, and a dielectric structure adjacent to sidewalls of the control gates, wherein a distance between an edge of the dielectric structure and an edge of the support structure 215 is less than a nanometer. Another aspect of the present disclosure provides a reticle comprising a first edge and a second edge opposite the first edge, a first pattern proximate the first edge, the first pattern comprising a first side parallel to the first edge and a second side connected to the first side and perpendicular to the first edge, the second side having a dimension in a range from 345 nm to 375 nm, and a second pattern proximate the second edge, the second pattern comprising a first side parallel to the second edge and a second side connected to the first side of the second pattern and perpendicular to the second edge, the second side of the second pattern having a dimension in a range from 345 nm to 375 nm, wherein the reticle is configured to be included in a system for forming a support structure for a memory device