CN-114613415-B - Nonvolatile memory, memory system and data erasing method of memory

Abstract

A nonvolatile memory, a memory system, and a data erasing method of the memory are provided, the method including applying a first turn-on voltage to memory cells included in a first stack of a plurality of stacks to be erased, applying source and drain erase voltages to a common source and drain, respectively, after the first turn-on voltage is applied, and applying a first voltage to dummy memory cells included in a second stack of the plurality of stacks to be erased during a step up of levels of the source and drain erase voltages to peak levels thereof.

Inventors

• WANG JUNBAO
• YOU KAIKAI
• LI KAIWEI
• Jia Jianquan
• ZHANG AN

Assignees

• 长江存储科技有限责任公司
• 长江存储科技有限责任公司

Dates

Publication Date

20260421

Application Date

20220303

Priority Date

20220303

Claims (20)

1. 1. A data erasing method of a nonvolatile memory, wherein the nonvolatile memory includes a plurality of memory blocks, each of the memory blocks including a plurality of stacks electrically connected to each other, each of the stacks including a plurality of memory cells and at least one dummy memory cell adjacent to an end of the stack, at least one stack having a plurality of drains at one end and a common source at one end of the other stack, the method comprising: Applying a first turn-on voltage to memory cells included in a first stack of the plurality of stacks to be erased; Applying a source erase voltage and a drain erase voltage to the common source and the drain, respectively, after applying the first turn-on voltage, and During the step of the source erase voltage and the drain erase voltage rising to their peak levels, a first voltage for inducing a gate induced drain leakage current is applied on a dummy memory cell included in a second stack of the plurality of stacks to be erased.
2. 2. The method of claim 1, further comprising: After the level of the first turn-on voltage rises to its peak level, the memory cell included in the first stack is set to a floating state.
3. 3. The method of claim 1, further comprising: after the level of the first turn-on voltage rises to its peak level, a first bias voltage is applied to memory cells included in the first stack.
4. 4. The method of claim 1, further comprising: a ground voltage is applied to a memory cell included in the second stack.
5. 5. The method of claim 1, wherein the second stack comprises a top stack comprising a plurality of drain select gates, the method further comprising: During the step of the source erase voltage and the drain erase voltage rising to their peak levels, a second voltage smaller than the drain erase voltage is applied to at least one of the drain select gates.
6. 6. The method of claim 1, wherein the first stack comprises a top stack comprising a drain select gate, the method further comprising: applying a second turn-on voltage to the drain select gate while applying the first turn-on voltage, and After the level of the second turn-on voltage climbs to its peak level, the drain select gate is set to a floating state or a second bias voltage is applied to the drain select gate.
7. 7. The method of claim 1, wherein the first stack comprises a bottom stack comprising a source select gate, the method further comprising: applying a third on voltage to the source select gate while applying the first on voltage, and After the level of the third turn-on voltage climbs to its peak level, the source select gate is set to a floating state or a third bias voltage is applied to the source select gate.
8. 8. A data erasing method for a nonvolatile memory, wherein the nonvolatile memory includes a plurality of memory blocks, each of the memory blocks including a plurality of stacks electrically connected to each other, each of the stacks including a plurality of memory cells and at least one dummy memory cell adjacent to an end of the stack, one end of at least one stack including a plurality of drains, and one end of at least one other stack including a common source, the method comprising: Applying a first turn-on voltage to memory cells included in a first stack of the plurality of stacks to be erased; Applying a holding voltage to a dummy memory cell included in a second stack of the plurality of stacks to be erased; Applying a source erase voltage and a drain erase voltage to the common source and the drain, respectively, after applying the first turn-on voltage and the hold voltage, and The retention voltage of the dummy memory cell is released during the step up of the levels of the source erase voltage and the drain erase voltage to their peak levels.
9. 9. The method of claim 8, further comprising: After the level of the first turn-on voltage rises to its peak level, the memory cell included in the first stack is set to a floating state.
10. 10. The method of claim 8, further comprising: after the level of the first turn-on voltage rises to its peak level, a first bias voltage is applied to memory cells included in the first stack.
11. 11. The method of claim 8, further comprising: a ground voltage is applied to a memory cell included in the second stack.
12. 12. The method of claim 8, wherein the second stack comprises a top stack comprising a plurality of drain select gates, the method further comprising: During the step of the source erase voltage and the drain erase voltage rising to their peak levels, a second voltage smaller than the drain erase voltage is applied to at least one of the drain select gates.
13. 13. The method of claim 8, wherein the first stack comprises a top stack comprising a drain select gate, the method further comprising: applying a second turn-on voltage to the drain select gate while applying the first turn-on voltage, and After the level of the second turn-on voltage climbs to its peak level, the drain select gate is set to a floating state or a second bias voltage is applied to the drain select gate.
14. 14. The method of claim 8, wherein the first stack comprises a bottom stack comprising a source select gate, the method further comprising: applying a third on voltage to the source select gate while applying the first on voltage, and After the level of the third turn-on voltage climbs to its peak level, the source select gate is brought into a floating state or a third bias voltage is applied to the source select gate.
15. 15. A non-volatile memory, comprising: A memory block including a plurality of stacks electrically connected to each other, each of the stacks including a plurality of memory cells and at least one dummy memory cell adjacent to an end of the stack, one end of at least one stack including a plurality of drains, and one end of at least one other stack including a common source; a plurality of word lines, each word line coupled to memory cells of a same row; a plurality of dummy word lines, each coupled to dummy memory cells of a same row; Bit lines coupled to the respective drains, and Peripheral circuitry coupled with the word line, the dummy word line, the bit line, and the common source and configured to: Applying a first turn-on voltage to memory cells included in a first stack of the plurality of stacks to be erased; Applying a source erase voltage and a drain erase voltage to the common source and the drain, respectively, after applying the first turn-on voltage, and During the step of the source erase voltage and the drain erase voltage rising to their peak levels, a first voltage for inducing a gate induced drain leakage current is applied on a dummy memory cell included in a second stack of the plurality of stacks to be erased.
16. 16. The non-volatile memory of claim 15, wherein the peripheral circuitry is further configured to: After the level of the first turn-on voltage rises to its peak level, the memory cell included in the first stack is set to a floating state.
17. 17. The non-volatile memory of claim 15, wherein the peripheral circuitry is further configured to: after the level of the first turn-on voltage rises to its peak level, a first bias voltage is applied to memory cells included in the first stack.
18. 18. A non-volatile memory, comprising: A memory block including a plurality of stacks electrically connected to each other, each of the stacks including a plurality of memory cells and at least one dummy memory cell adjacent to an end of the stack, one end of at least one stack including a plurality of drains, and one end of at least one other stack including a common source; a plurality of word lines, each word line coupled to memory cells of a same row; a plurality of dummy word lines, each coupled to dummy memory cells of a same row; Bit lines coupled to the respective drains, and Peripheral circuitry coupled with the word line, the dummy word line, the bit line, and the common source and configured to: Applying a first turn-on voltage to memory cells included in a first stack of the plurality of stacks to be erased; Applying a holding voltage to a dummy memory cell included in a second stack of the plurality of stacks to be erased; Applying a source erase voltage and a drain erase voltage to the common source and the drain, respectively, after applying the first turn-on voltage and the hold voltage, and The retention voltage of the dummy memory cell is released during the step up of the levels of the source erase voltage and the drain erase voltage to their peak levels.
19. 19. The non-volatile memory of claim 18, wherein the peripheral circuitry is further configured to: After the level of the first turn-on voltage rises to its peak level, the memory cell included in the first stack is set to a floating state.
20. 20. The non-volatile memory of claim 18, wherein the peripheral circuitry is further configured to: after the level of the first turn-on voltage rises to its peak level, a first bias voltage is applied to memory cells included in the first stack.

Description

Nonvolatile memory, memory system and data erasing method of memory Technical Field The application relates to the technical field of semiconductors. In particular, the present application relates to a nonvolatile memory, a memory system, and a data erasing method of the memory. Background Recently, nonvolatile memory having vertical memory cells is widely used in electronic devices, which generally include a plurality of stacks (also referred to as a plurality deck) vertically. The problem of reduced channel current is particularly pronounced as the number of layers of the non-volatile memory increases, and in order to solve this problem, electron-rich conductive plugs are typically provided between the stacks. It should be appreciated that this background section is intended to provide, in part, a useful background for understanding the technology, however, that such content does not necessarily fall within the knowledge or understanding of one of skill in the art prior to the filing date of the present application. Disclosure of Invention An aspect of the present application provides a data erasing method for a nonvolatile memory, wherein the nonvolatile memory includes a plurality of memory blocks, each of the memory blocks including a plurality of stacks electrically connected to each other, each of the stacks including a plurality of memory cells and at least one dummy memory cell adjacent to an end of the stack, at least one of the stacks having a plurality of drains at one end and at least another of the stacks having a common source, the method including applying a first on voltage to memory cells included in a first stack of the plurality of stacks to be erased, applying source and drain erase voltages to the common source and the drain, respectively, after the first on voltage is applied, and applying a first voltage to dummy memory cells included in a second stack of the plurality of stacks to be erased during a level ramp up of the source and drain erase voltages to a peak level thereof. In one embodiment of the present application, the first voltage applied is a sensing voltage that senses a drain leakage current by a sensing gate. In one embodiment of the present application, the method further includes setting the memory cell included in the first stack to a floating state after the level of the first turn-on voltage is ramped up to its peak level. In one embodiment of the present application, the method further includes applying a first bias voltage to the memory cells included in the first stack after the level of the first turn-on voltage climbs to its peak level. In one embodiment of the application, the method further comprises applying a ground voltage to the memory cells comprised by the second stack. In one embodiment of the present application, the second stack comprises a top stack comprising a plurality of drain select gates, the method further comprising applying a second voltage less than the drain erase voltage at least one of the drain select gates during the step up of the source erase voltage and the drain erase voltage to their peak levels. In one embodiment of the present application, the first stack includes a top stack including a drain select gate, the method further includes applying a second on voltage to the drain select gate while the first on voltage is applied, and setting the drain select gate to a floating state or applying a second bias voltage to the drain select gate after a level of the second on voltage rises to its peak level. In one embodiment of the present application, the first stack includes a bottom stack including a source select gate, the method further includes applying a third on voltage to the source select gate while the first on voltage is applied, and setting the source select gate to a floating state or applying a third bias voltage to the source select gate after a level of the third on voltage rises to its peak level. Another aspect of the present application provides another data erasing method for a nonvolatile memory, wherein the nonvolatile memory includes a plurality of memory blocks, each of the memory blocks includes a plurality of stacks electrically connected to each other, each of the stacks includes a plurality of memory cells and at least one dummy memory cell adjacent to an end of the stack, one end of at least one stack includes a plurality of drains, and one end of at least another stack includes a common source, the method includes applying a first on voltage to memory cells included in a first stack of the plurality of stacks to be erased, applying a holding voltage to dummy memory cells included in a second stack of the plurality of stacks to be erased, applying a source erase voltage and a drain erase voltage to the common source and the drains, respectively, after the first on voltage and the holding voltage are applied, and releasing the holding voltage of the dummy memory cells during a step up of the levels of the so