CN-114628277-B - Method and system for managing overlay alignment and computing system

Abstract

A method and system for managing overlay alignment and a computing system. The present disclosure describes techniques for managing vertical alignment or overlap in semiconductor manufacturing using machine learning. Alignment of interconnect features in a fan-out wafer level packaging process is assessed and managed by the disclosed techniques. Big data and machine learning are used to train classifications that relate overlapping error source factors to overlapping metrology categories. The overlay error source factor comprises a tool signal. The training class includes a base class and a meta class.

Inventors

• LIN ZICHENG
• LIU ZIZHENG
• LI MINGTAN
• ZUO KEWEI
• WANG QINGRONG

Assignees

• 台湾积体电路制造股份有限公司

Dates

Publication Date

20260512

Application Date

20210420

Priority Date

20210225

Claims (18)

1. 1. A method of managing overlay alignment, comprising: determining a tool signal for a wafer processing tool that forms a first feature on a first wafer; Determining a first value of an overlap metric for the first feature; generating a first data set comprising the tool signal and the first value of the overlay metrology; Generating a classification relating the tool signal and the overlay metrology based on the first dataset, the classification comprising a base classification and a meta classification, wherein the base classification is trained to take as output an estimated overlay metrology value, the meta classification is trained to take as input the estimated overlay metrology value of the base classification and take as output an actual overlay metrology measurement, and the base classification and the meta classification are trained with different subsets of data of the first dataset, and The classification is used to estimate a second value of the overlay metrology for a second feature on a second wafer.
2. 2. The method of claim 1, wherein in training the meta-classification, an output of the base classification for training a subset of data of a meta-classification is taken as an input to the meta-classification.
3. 3. The method of claim 1, wherein the first data set is randomly assigned to a training data set and a validation data set, the base classification is generated based on the training data set, and the meta classification is generated based on the validation data set.
4. 4. The method of claim 3, further comprising determining an fitness score of the classification using a test dataset that is part of the first dataset.
5. 5. The method of claim 1, wherein the tool signal is a difference between a signal of the wafer processing tool when the first feature is formed on the first wafer and a reference signal of the wafer processing tool.
6. 6. The method of claim 5 wherein the reference signal is a historical signal of the wafer processing tool that forms a feature on a wafer having a historically minimum magnitude of overlay error.
7. 7. The method of claim 6, wherein the reference signal is dynamically determined.
8. 8. The method of claim 1, wherein the base classification is a random forest model classification.
9. 9. The method of claim 1, wherein the meta classification is an inverse distance weighted k nearest neighbor regression.
10. 10. The method of claim 1, further comprising adjusting operation of the wafer processing tool based on the estimated second value of the overlay metrology.
11. 11. The method of claim 10, wherein the adjusting the operation of the wafer processing tool is based on estimated overlap metrics for a plurality of regions on the second wafer.
12. 12. The method of claim 11, wherein the estimated overlap metric value for one of the plurality of regions is an average of one or more estimated second values of the overlap metric over one or more second features within the region.
13. 13. A system for managing overlay alignment, comprising: A wafer processing tool operable to form a plurality of features on a wafer, the plurality of features including a first subset of features positioned in a first region on the wafer and a second subset of features positioned in a second region on the wafer; a metrology tool operable to measure a plurality of overlay metrology values of the plurality of features on the wafer; an overlay modeling tool operable to generate a plurality of estimated overlay metrology values of the plurality of features based on tool signal data of the wafer processing tool, wherein the overlay modeling tool is operable to generate a classification relating the tool signal data to the overlay metrology values of features on the wafer, wherein the classification comprises a plurality of base classifications and a meta classification, an output of the plurality of base classifications being an input of the meta classification, and A process control tool operable to adjust operation of the wafer processing tool based on a first zone-based adjustment value of the first zone and a second zone-based adjustment value of the second zone, the first zone-based adjustment value being based on an estimated overlay metric value of the first feature subset and the second zone-based adjustment value being based on an estimated overlay metric value of the second feature subset.
14. 14. The system of claim 13, wherein the first region and the second region are concentric with each other.
15. 15. The system of claim 13, wherein the first region-based adjustment value is an average of the estimated overlap metric values of the first feature subset and the second region-based adjustment value is an average of the estimated overlap metric values of the second feature subset.
16. 16. A computing system, comprising: Processor, and A storage unit having stored thereon executable instructions that, when executed by the processor, configure the processor to perform actions comprising: receiving data regarding a tool signal of a wafer processing tool that forms a first feature on a first wafer; Receiving data of an overlay metrology of the first feature; Generating a data pool containing the data of the tool signal and the data of the overlay metrology; Learning a stacked classification comprising a first classification and a second classification, the first classification and the second classification being learned based on a first subset of data from the data pool and a second subset of data different from the first subset of data, wherein the first classification is trained to take as output an estimated overlap metric value and the second classification is trained to take as input the estimated overlap metric value and take as output an actual overlap metric measurement, and The stack classification is used to estimate an overlay metrology of a second feature on a second wafer.
17. 17. The computing system of claim 16, wherein the first classification correlates the tool signal and the overlay metrology.
18. 18. The computing system of claim 17, wherein the learning the second classification includes: generating estimated overlay metrology data by applying tool signal data of the second subset of data to the first classification, and The second classification is learned based on the estimated overlapping metric data and overlapping metric data of the second subset of data.

Description

Method and system for managing overlay alignment and computing system Technical Field The techniques set forth in embodiments of the present invention relate generally to alignment or overlay in semiconductor manufacturing, and more particularly, to methods and systems and computing systems that manage overlay alignment. Background As semiconductor technology evolves, semiconductor die become smaller and smaller while more and more functionality is integrated into a single die. Thus, there is a need to include an ever greater number of I/O pads and smaller areas of die surface in integrated circuit (INTEGRATED CIRCUIT; IC) packages. Fan-out wafer level packaging (WAFER LEVEL PACKAGING; WLP) is a promising packaging technology to address this challenging situation. In fan-out WLP, the die is severed from the initial front end die prior to positioning on the carrier die for packaging using connection routing and I/O pads. In a fan-out WLP process, an advantage is that the I/O pads associated with the die may be redistributed to a larger area than the surface of the die itself. Thus, the number of I/O pads packaged with the die may be increased. Fan-out WLP packages may be used to package one die, multiple dies side-by-side, or multiple dies in a package-on-package (POP) vertical configuration. POP configuration in fan-out WLP is achieved by interconnecting features (e.g., vias) that vertically connect multiple dies. For example, under integrated fan-out InFO technology, inFO _pop architecture is a package containing DRAM die connected by InFO through-holes (TIVs), while InFO _m package contains one or more die that can be placed side-by-side, such as logic die and memory die. Overlay metrology processes are used to monitor and control vertical alignment in various semiconductor manufacturing processes. Overlay metrology generally specifies the accuracy of alignment (e.g., vertical alignment) of a first patterned layer or a feature thereon relative to a second patterned layer disposed at a different vertical level than the first patterned layer. Overlay error refers to misalignment between a first portion on a first patterned layer and a second portion on a second patterned layer. Overlay error measurements (e.g., measurements) may be measured based on an offset between the first portion and the second portion or between an actual position of the first portion and a target position of the first portion. The target position may be determined based on advanced process control (advanced process control; APC) in wafer processing. In fan-out WLP, the tested good die are positioned onto a carrier wafer. The interconnect feature layer is formed to connect the die to the associated I/O pads and among the various interconnect layers themselves. The interconnect is formed by a wafer level process in which photoresist and photolithography processes are similarly used as in the front end wafer fabrication process. Thus, there is a need to manage vertical alignment between or among successive interconnect layers. Disclosure of Invention An embodiment of the present invention provides a method of managing overlay alignment comprising determining a tool signal for a wafer processing tool that forms a first feature on a first wafer, determining a first value of an overlay metrology for the first feature, generating a first dataset comprising the tool signal and the first value of the overlay metrology, generating a classification based on the first dataset relating the tool signal and the overlay metrology, the classification comprising a base classification and a meta-classification, and estimating a second value of the overlay metrology for a second feature on a second wafer using the classification. Embodiments of the present invention provide a system for managing overlay alignment comprising a wafer processing tool operable to form a plurality of features on a wafer, the plurality of features including a first subset of features positioned in a first region on the wafer and a second subset of features positioned in a second region on the wafer, a metrology tool operable to measure a plurality of overlay metrology values of the plurality of features on the wafer, an overlay modeling tool operable to generate a plurality of estimated overlay metrology values of the plurality of features based on tool signal data of the wafer processing tool, and a process control tool operable to adjust operation of the wafer processing tool based on a first region-based adjustment value and a second region-based adjustment value of the first region, the first region-based adjustment value being based on the estimated overlay metrology values of the first subset of features, and the second region-based adjustment value being based on the estimated overlay metrology values of the second subset of features. Embodiments of the present invention provide a computing system including a processor and a storage unit having stored thereon executabl