CN-114639420-B - Enhanced gradient seeding scheme during programming operations in memory subsystems

Abstract

The present disclosure relates to an enhanced gradient seeding scheme during a programming operation in a memory subsystem. Control logic in the memory device initiates a programming operation on the memory array, the programming operation including a seeding phase. During the seeding phase, the control logic causes a seeding voltage to be applied to a string of memory cells in a data block of the memory array during the seeding phase of the programming operation and causes a first positive voltage to be applied to a first plurality of word lines of the data block during the seeding phase, wherein each of the first plurality of word lines is coupled to a corresponding memory cell in a first plurality of memory cells in the string of memory cells, the first plurality of word lines including a selected word line associated with the programming operation. The control logic further causes a second positive voltage to be applied to one or more second word lines coupled to one or more second memory cells on a source side of the first plurality of memory cells in the string of memory cells during the seeding stage, wherein the second positive voltage is less than the first positive voltage.

Inventors

• V.Q.Ye
• Lu Jinghuang
• Y.Dong

Assignees

• 美光科技公司

Dates

Publication Date

20260512

Application Date

20211215

Priority Date

20201216

Claims (20)

1. 1. A memory device, comprising: memory array, and Control logic operatively coupled with the memory array to perform operations comprising: Initiating a programming operation on the memory array, the programming operation including a seeding phase; causing a seeding voltage to be applied to a string of memory cells in a data block of the memory array during the seeding phase of the programming operation; Such that a first positive voltage is applied to a first plurality of word lines of the data block during the seeding phase, wherein each of the first plurality of word lines is coupled to a corresponding memory cell of a first plurality of memory cells in the string of memory cells, the first plurality of word lines including a selected word line associated with the programming operation, at least one word line being adjacent to the selected word line on a drain side of the selected word line and at least one word line being adjacent to the selected word line on a source side of the selected word line, and Such that a second positive voltage is applied to one or more second word lines coupled to one or more second memory cells on a source side of the first plurality of memory cells in the string of memory cells during the seeding stage, wherein the second positive voltage is less than the first positive voltage.
2. 2. The memory device of claim 1, wherein the selected word line is coupled to a first memory cell of the first plurality of memory cells, and wherein causing the first positive voltage to be applied to the first plurality of word lines of the block of data comprises: such that the first positive voltage is applied to one or more third word lines of the first plurality of word lines that are coupled to one or more of the first plurality of memory cells on a drain side of the first memory cells in the string of memory cells.
3. 3. The memory device of claim 2, wherein causing the first positive voltage to be applied to the first plurality of word lines of the data block comprises: such that the first positive voltage is applied to one or more fourth word lines of the first plurality of word lines that are coupled to one or more of the first plurality of memory cells on a source side of the first memory cells in the string of memory cells.
4. 4. The memory device of claim 3, wherein the control logic is to perform operations further comprising: Such that a third positive voltage is applied to one or more fifth word lines coupled to one or more third memory cells on the source side of the one or more second memory cells in the string of memory cells during the seeding stage, wherein the third positive voltage is less than the second positive voltage.
5. 5. The memory device of claim 4, wherein the control logic is to perform operations further comprising: Such that a ground voltage is applied to a second plurality of word lines of the data block during the seeding stage, wherein each of the second plurality of word lines is coupled to a corresponding memory cell of a second plurality of memory cells in the string, wherein the second plurality of memory cells is adjacent to the one or more third memory cells on the source side of the string of memory cells.
6. 6. The memory device of claim 5, wherein the control logic is to perform operations further comprising: Such that respective bias voltages are applied to word lines coupled to one or more inactive memory cells on drain sides of the first plurality of memory cells in the string of memory cells and select gate devices during the seeding stage.
7. 7. The memory device of claim 6, wherein the control logic is to perform operations further comprising: So that the first positive voltage applied to the selected word line and to the one or more third word lines ramps down to an intermediate voltage at the end of the seeding stage, wherein the intermediate voltage is less than the first positive voltage and greater than the ground voltage, and Such that the first positive voltage applied to the one or more fourth word lines, the second positive voltage applied to the one or more second word lines, and the third positive voltage applied to the one or more fifth word lines ramp down to the ground voltage at the end of the seeding stage.
8. 8. The memory device of claim 7, wherein the control logic is to perform operations further comprising: such that the respective bias voltages applied to the word lines coupled to the select gate device and the one or more inactive memory cells ramp down to the ground voltage after a delay period at the end of the seeding stage, wherein the delay period includes a period of time after the first, second, and third positive voltages have ramped down to at least one of the intermediate voltage or the ground voltage.
9. 9. A method for a memory device, comprising: Initiating a programming operation on the memory array, the programming operation including a seeding phase; causing a seeding voltage to be applied to a string of memory cells in a data block of the memory array during the seeding phase of the programming operation; Such that a first positive voltage is applied to a first plurality of word lines of the data block during the seeding phase, wherein each of the first plurality of word lines is coupled to a corresponding memory cell of a first plurality of memory cells in the string of memory cells, the first plurality of word lines including a selected word line associated with the programming operation, at least one word line being adjacent to the selected word line on a drain side of the selected word line and at least one word line being adjacent to the selected word line on a source side of the selected word line, and Such that a second positive voltage is applied to one or more second word lines coupled to one or more second memory cells on a source side of the first plurality of memory cells in the string of memory cells during the seeding stage, wherein the second positive voltage is less than the first positive voltage.
10. 10. The method of claim 9, wherein the selected word line is coupled to a first memory cell of the first plurality of memory cells, and wherein causing the first positive voltage to be applied to the first plurality of word lines of the block of data comprises: such that the first positive voltage is applied to one or more third word lines of the first plurality of word lines that are coupled to one or more of the first plurality of memory cells on a drain side of the first memory cells in the string of memory cells.
11. 11. The method of claim 10, wherein causing the first positive voltage to be applied to the first plurality of word lines of the data block comprises: such that the first positive voltage is applied to one or more fourth word lines of the first plurality of word lines that are coupled to one or more of the first plurality of memory cells on a source side of the first memory cells in the string of memory cells.
12. 12. The method of claim 11, further comprising: Such that a third positive voltage is applied to one or more fifth word lines coupled to one or more third memory cells on the source side of the one or more second memory cells in the string of memory cells during the seeding stage, wherein the third positive voltage is less than the second positive voltage.
13. 13. The method of claim 12, further performing comprising: Such that a ground voltage is applied to a second plurality of word lines of the data block during the seeding stage, wherein each of the second plurality of word lines is coupled to a corresponding memory cell of a second plurality of memory cells in the string, wherein the second plurality of memory cells is adjacent to the one or more third memory cells on the source side of the string of memory cells.
14. 14. The method of claim 13, further comprising: Such that respective bias voltages are applied to word lines coupled to one or more inactive memory cells on drain sides of the first plurality of memory cells in the string of memory cells and select gate devices during the seeding stage.
15. 15. The method of claim 14, further comprising: So that the first positive voltage applied to the selected word line and to the one or more third word lines ramps down to an intermediate voltage at the end of the seeding stage, wherein the intermediate voltage is less than the first positive voltage and greater than the ground voltage, and Such that the first positive voltage applied to the one or more fourth word lines, the second positive voltage applied to the one or more second word lines, and the third positive voltage applied to the one or more fifth word lines ramp down to the ground voltage at the end of the seeding stage.
16. 16. The method of claim 15, further comprising: such that the respective bias voltages applied to the word lines coupled to the select gate device and the one or more inactive memory cells ramp down to the ground voltage after a delay period at the end of the seeding stage, wherein the delay period includes a period of time after the first, second, and third positive voltages have ramped down to at least one of the intermediate voltage or the ground voltage.
17. 17. A memory device, comprising: A first string of memory cells in a first sub-block of a block of memory cells, the first sub-block including a selected sub-block, wherein the first string of memory cells includes a first plurality of memory cells coupled to a plurality of word lines, and A second memory cell string in a second sub-block of the memory cell block, the second sub-block comprising a non-selected sub-block, wherein the second memory cell string comprises a second plurality of memory cells coupled to the plurality of word lines coupled to the first memory cell string, wherein a first subset of the plurality of word lines is configured to receive a first positive voltage signal during a seeding phase of a programming operation performed on the selected sub-block, wherein each of the first subset of the plurality of word lines is coupled to a corresponding memory cell of a first subset of the second plurality of memory cells in the second memory cell string, the first subset of the plurality of word lines comprising a selected word line associated with the programming operation, at least one word line being adjacent to the selected word line on a drain side of the selected word line, and at least one word line being adjacent to the selected word line on a source side of the selected word line, and wherein one or more second word lines are configured to receive a second positive voltage signal during the programming phase of the second subset of the plurality of memory cells in the second memory cell string.
18. 18. The memory device of claim 17, wherein one or more third word lines adjacent to the one or more second word lines are configured to receive a third positive voltage, wherein the one or more third word lines adjacent to the one or more second word lines are coupled to one or more of the second plurality of memory cells on a source side of the memory cells coupled to the one or more second word lines, wherein the third positive voltage is less than the second positive voltage.
19. 19. The memory device of claim 18, wherein a first portion of the first subset of the plurality of word lines is configured to ramp the first positive voltage signal applied during the seeding stage to an intermediate voltage signal at the end of the seeding stage, wherein the intermediate voltage signal is less than the first positive voltage signal and greater than a ground voltage signal, and wherein a second portion of the first subset of the plurality of word lines is configured to ramp the first positive voltage signal applied during the seeding stage to the ground voltage at the end of the seeding stage.
20. 20. The memory device of claim 19, wherein word lines coupled to one or more inactive memory cells in the string of select gate devices and the second memory cells are configured to ramp down respective voltage signals applied during the seeding stage to the ground voltage after a delay period at the end of the seeding stage, wherein the delay period comprises a period of time after the first positive voltage has ramped down to at least one of the intermediate voltage or the ground voltage.

Description

Enhanced gradient seeding scheme during programming operations in memory subsystems Technical Field Embodiments of the present disclosure relate generally to memory subsystems and, more particularly, to an enhanced gradient seeding scheme during programming operations in memory subsystems. Background The memory subsystem may include one or more memory devices that store data. The memory device may be, for example, a nonvolatile memory device and a volatile memory device. In general, a host system may utilize a memory subsystem to store data at and retrieve data from a memory device. Disclosure of Invention In one aspect, the present disclosure relates to a memory device comprising a memory array and control logic operatively coupled with the memory array to perform operations comprising initiating a programming operation on the memory array, the programming operation comprising a seeding phase, causing a seeding voltage to be applied to a string of memory cells in a data block of the memory array during the seeding phase of the programming operation, causing a first positive voltage to be applied to a first plurality of word lines of the data block during the seeding phase, wherein each of the first plurality of word lines is coupled to a corresponding memory cell of a first plurality of memory cells in the string of memory cells, the first plurality of word lines comprising a selected word line associated with the programming operation, and causing a second positive voltage to be applied to one or more second word lines coupled to one or more second memory cells on a source side of the first plurality of memory cells in the string of memory cells during the seeding phase, wherein the second positive voltage is less than the first positive voltage. In another aspect, the present disclosure is directed to a method comprising initiating a programming operation on a memory array, the programming operation comprising a seeding phase, causing a seeding voltage to be applied to a string of memory cells in a data block of the memory array during the seeding phase of the programming operation, causing a first positive voltage to be applied to a first plurality of word lines of the data block during the seeding phase, wherein each of the first plurality of word lines is coupled to a corresponding memory cell of a first plurality of memory cells in the string of memory cells, the first plurality of word lines comprising a selected word line associated with the programming operation, and causing a second positive voltage to be applied to one or more second word lines coupled to one or more second memory cells on a source side of the first plurality of memory cells in the string of memory cells during the seeding phase, wherein the second positive voltage is less than the first positive voltage. In another aspect, the present disclosure relates to a memory device comprising a first memory cell string in a first sub-block of a memory cell block, the first sub-block comprising a selected sub-block, wherein the first memory cell string comprises a first plurality of memory cells coupled to a plurality of word lines, and a second memory cell string in a second sub-block of the memory cell block, the second sub-block comprising a non-selected sub-block, wherein the second memory cell string comprises a second plurality of memory cells coupled to the plurality of word lines coupled to the first memory cell string, wherein a first subset of the plurality of word lines is configured to receive a first positive voltage signal during a seeding phase of a programming operation performed on the selected sub-block, wherein each of the first subset of the plurality of word lines is coupled to a corresponding memory cell of a first subset of the second plurality of memory cells in the second memory cell string, the first subset of the plurality of word lines comprises a second plurality of memory cells coupled to the first word line, wherein the first subset of the plurality of word lines comprises a second word line coupled to the first word line during the first phase of the programming operation, wherein the first subset of the plurality of word lines is configured to receive a positive voltage signal during the first phase of the programming operation or the first subset of the plurality of word lines. Drawings The present disclosure will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the disclosure. FIG. 1 illustrates an example computing system including a memory subsystem, according to some embodiments of the disclosure. FIG. 2A is a block diagram of a memory device in communication with a memory subsystem controller of a memory subsystem, according to an embodiment. Fig. 2B is a schematic diagram illustrating a string of memory cells in a data block of a memory device in a memory subsystem according to some embodiments of the present disclosure.