CN-114649022-B - Apparatus and method for line hammer based cache locking

Abstract

Apparatus, systems, and methods for line hammer based cache locking. The controller of the memory may include an aggressor detector circuit that determines whether the address is an aggressor address. The controller may include a tracker circuit that may count a number of times an address is identified as an aggressor and may determine whether the aggressor address is a frequent aggressor address based on the count. If the address is a frequent aggressor address, then the cache entry associated with the frequent aggressor address may be locked (e.g., within a set amount of time). In some embodiments, the controller may include a second tracker that may determine whether the frequent aggressor address is a high attack address. The address map associated with the high attack address may be changed.

Inventors

• David A Robles

Assignees

• 美光科技公司
• 美光科技公司

Dates

Publication Date

20260421

Application Date

20211129

Priority Date

20201218

Claims (20)

1. 1. A memory controller apparatus, comprising: a processor configured to provide an address to a memory and receive data associated with the address; Logic configured to identify a row of the memory associated with the address, change a count value associated with the address, and determine that the row of the memory associated with the address has been activated at least a threshold number of times based on the count value, and A cache configured to store data associated with the address and configured to manage the data stored in the cache based at least in part on the line having been activated at least the threshold number of times.
2. 2. The memory controller apparatus of claim 1, wherein the logic is further configured to identify the row of the memory associated with the address based in part on a determination that the row of the memory has been activated at least a second threshold number of times, wherein the second threshold number of times is less than the threshold number of times.
3. 3. The memory controller apparatus of claim 1, wherein the cache is configured to evict data from the cache based on one or more criteria, and wherein the cache manages the stored data by preventing eviction of the stored data based at least in part on the line having been activated at least the threshold number of times.
4. 4. The memory controller device of claim 3, wherein the cache is configured to prevent eviction of the stored data for at least a set amount of time.
5. 5. The memory controller apparatus of claim 1, wherein the logic is further configured to determine whether the row of the memory associated with the address has been activated at least a second threshold number of times and associate the address with a second row instead of the row when the address has been activated at least the second threshold number of times.
6. 6. The memory controller apparatus of claim 5, wherein the logic is further configured to change a second count value, and wherein the logic is configured to determine whether the row of the memory associated with the address has been activated at least a second threshold number of times based at least in part on the second count value.
7. 7. The memory controller apparatus of claim 5, wherein the row includes a first type of memory cell, and wherein the second row includes a second type of memory cell different from the first type of memory cell.
8. 8. A memory system, comprising: memory, and A controller configured to operate the memory, the controller comprising: a processor configured to provide an address as part of an access operation; Logic configured to identify a row of the memory associated with the address and change a count value associated with the address and determine that the row of the memory associated with the address has been activated at least a threshold number of times based on the count value, and A cache configured to store data associated with the address retrieved from the memory and configured to manage the data stored in the cache based at least in part on the line having been activated at least the threshold number of times.
9. 9. The memory system of claim 8, wherein the logic is configured to identify the row of the memory associated with the address based at least in part on the row having been activated at least a second threshold number of times.
10. 10. The memory system of claim 8, wherein the cache is configured to manage the stored data by maintaining the stored data in the cache for at least a set amount of time.
11. 11. The memory system of claim 8, wherein the logic is further configured to determine whether the row of the memory associated with the address has been activated at least a second threshold number of times, and wherein the address is associated with a second row other than the row based at least in part on the row having been activated at least the second threshold number of times.
12. 12. The memory system of claim 11, wherein the memory includes a first region and a second region, and wherein the row is in the first region and the second row is in the second region.
13. 13. The memory system of claim 12, wherein the first region includes a first type of stripe, and wherein the second region includes a second type of stripe.
14. 14. The memory system of claim 12, wherein the first region includes a first type of memory cells and the second region includes a second type of memory cells.
15. 15. A method for performing memory controller operations, comprising: Identifying a row of memory associated with the address; Compare the address with a plurality of stored addresses and change a count value based in part on the comparison; Determining whether the row of the memory has been accessed at least a threshold number of times based in part on the count value, and A cache entry associated with the address is managed based in part on a determination that the line of the memory has been accessed at least the threshold number of times.
16. 16. The method as recited in claim 15, further comprising: determining whether the row of the memory has been accessed at least a second threshold number of times, and The correlation of the addresses is changed to the second row of the memory.
17. 17. The method as recited in claim 16, further comprising: Comparing the address with a second plurality of stored addresses and changing a second count value based in part on the comparing, and Determining whether the row of the memory has been accessed at least the second threshold number of times based in part on the second count value.
18. 18. The method as recited in claim 16, further comprising: Comparing the count value with a first threshold to determine whether the memory has been accessed at least the threshold number of times, and The count value is compared to a second threshold to determine whether the memory has been accessed at least the second threshold number of times.
19. 19. The method of claim 16, further comprising changing the correlation of the addresses from a first memory region to a second memory region.
20. 20. The method of claim 15, further comprising managing the cache entry by maintaining data associated with the address in a cache for at least a set amount of time.

Description

Apparatus and method for line hammer based cache locking Technical Field The present disclosure relates generally to semiconductor devices, and more particularly, to semiconductor memory devices. Background In particular, the present disclosure relates to volatile memory, such as Dynamic Random Access Memory (DRAM). Information may be stored as physical signals on individual memory cells of the memory (e.g., charge on capacitive elements). The memory may be volatile memory and the physical signal may decay over time (which may degrade or destroy information stored in the memory cells). It may be necessary to periodically refresh the information in the memory cells by, for example, overwriting the information to restore the physical signal to an initial value. As the size of memory components decreases, the density of memory cells increases greatly. Various access patterns, commonly referred to as attacks (attack), to a particular memory cell or group of memory cells may result in an increase in the rate of data degradation in neighboring memory cells. As part of the targeted refresh operation, memory cells affected by the attack may be identified and refreshed. The controller of the memory and/or the memory itself may track access patterns to various memory addresses in order to determine whether it is involved in an attack so that it can be refreshed. However, it may be useful to take additional action to mitigate data degradation after refresh. Disclosure of Invention One embodiment of the present disclosure provides an apparatus comprising a processor configured to provide an address to a memory and receive data associated with the address, logic configured to identify a row of the memory associated with a particular address, change a count value associated with the particular address and determine that the row of the memory associated with the particular address has been activated at least a threshold number of times based on the count value, and a cache configured to store the data associated with the particular address and to manage the stored data in the cache based at least in part on the row having been activated at least the threshold number of times. Another embodiment of the present disclosure provides a system comprising a memory, and a controller configured to operate the memory, the controller comprising a processor configured to provide an address as part of an access operation, logic configured to identify a row of the memory associated with a particular address and change a count value associated with the particular address and determine that the row of the memory associated with the particular address has been activated at least a threshold number of times based on the count value, and a cache configured to store data retrieved from the memory associated with the particular address and configured to manage the stored data in the cache based at least in part on the row having been activated at least the threshold number of times. Yet another embodiment of the present disclosure provides a method comprising identifying a line of memory associated with a particular address, comparing the particular address to a plurality of stored addresses, and changing a count value based in part on the comparison, determining whether the line of memory has been accessed at least a threshold number of times based in part on the count value, and managing cache entries associated with the particular address based in part on the determination that the line of memory has been accessed at least the threshold number of times. Drawings Fig. 1 is a block diagram of a memory system according to some embodiments of the present disclosure. Fig. 2 is a block diagram of a semiconductor device according to an embodiment of the present disclosure. Fig. 3 is a block diagram of row hammer logic according to some embodiments of the present disclosure. Fig. 4 is a block diagram of a cache and cache logic according to some embodiments of the present disclosure. Fig. 5 is a block diagram of a method according to some embodiments of the present disclosure. Detailed Description The following description of certain embodiments is merely exemplary in nature and is in no way intended to limit the scope of the disclosure, its application, or uses. In the following detailed description of embodiments of the systems and methods of the present invention, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration specific embodiments in which the described systems and methods may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the presently disclosed systems and methods, and it is to be understood that other embodiments may be utilized and that structural and logical changes may be made without departing from the spirit and scope of the present disclosure. Moreover, for the sake of clarity, detailed descriptions o