CN-114649221-B - Method of manufacturing a semiconductor device and corresponding semiconductor device

Abstract

The present disclosure relates to a method of manufacturing a semiconductor device, such as a QFN/BGA flip-chip package, and a corresponding semiconductor device. For example, the method includes disposing one or more semiconductor chips or dies on the leadframe, the semiconductor chips or dies having a first side facing toward and electrically coupled to the leadframe and a second side facing away from the leadframe. The method further includes molding a package over the semiconductor chip disposed on the leadframe, wherein the package has an outer surface opposite the leadframe and includes a Laser Direct Structuring (LDS) material. A laser direct structuring process is applied to the LDS material of the package to provide metal vias between the outer surface of the package and the second side of the semiconductor chip and metal pads at the outer surface of the package.

Inventors

• M. De Lai
• D. Vitello

Assignees

• 意法半导体股份有限公司

Dates

Publication Date

20260505

Application Date

20211217

Priority Date

20201217

Claims (14)

1. 1. A method, comprising: disposing at least one semiconductor die on a leadframe, the at least one semiconductor die having a first side facing toward and electrically coupled to the leadframe and a second side facing away from the leadframe; molding a package over the at least one semiconductor die disposed on the leadframe, wherein the package has an outer surface opposite the leadframe and includes a Laser Direct Structuring (LDS) material; applying a laser direct structuring process to the LDS material of the package to: providing at least one metal via between the outer surface of the package and the second side of the at least one semiconductor die, and Metal pads are provided at the outer surface of the package, Wherein the laser direct structuring process applied to the LDS material of the package comprises: Applying laser energy to the outer surface of the package to drill at least one laser activated hole between the outer surface of the package and the second side of the at least one semiconductor die and provide laser activation of the outer surface of the package, and Forming a metal material: in the at least one laser activated hole to provide the at least one metal via between the outer surface of the package and the second side of the at least one semiconductor die, and The metal pads are provided at the outer surface of the package to provide the metal pads at the outer surface of the package.
2. 2. The method of claim 1, further comprising forming a metallization at the second side of the at least one semiconductor die, wherein the at least one metal via is coupled to the metallization.
3. 3. The method of claim 1, further comprising coupling the at least one metal via to a metallization formed on the second side of the at least one semiconductor die.
4. 4. The method of claim 1, further comprising electrically coupling the first side of the at least one semiconductor die with the leadframe via a metal pillar.
5. 5. The method of claim 1, further comprising: A laser direct structuring process is applied to the LDS material of the package to provide at least one metal via between the outer surface of the package and the leadframe, wherein the at least one metal via Kong Liyu forms the metal pad at the outer surface of the package.
6. 6. The method of claim 5, further comprising: applying a laser direct structuring process to the LDS material of the package to provide at least one sacrificial metal via between the outer surface of the package and the leadframe, wherein the at least one sacrificial metal via Kong Liyu forms the metal pad at the outer surface of the package, and After forming the metal pad at the outer surface of the package, the at least one sacrificial metal via is removed.
7. 7. A device, comprising: a leadframe having at least one semiconductor die disposed thereon, the at least one semiconductor die having a first side facing toward and electrically coupled to the leadframe and a second side remote from the leadframe; a package on the at least one semiconductor die disposed on the leadframe, wherein the package has an outer surface opposite the leadframe and includes a Laser Direct Structuring (LDS) material; At least one metal via formed in said LDS material of said package between said outer surface of said package and said second side of said at least one semiconductor die, and A metal pad formed at the outer surface of the LDS material of the package, Wherein the device further comprises a metallic material: Located in at least one laser activated hole drilled in the LDS material of the package to provide the at least one metal via between the outer surface of the package and the second side of the at least one semiconductor die, and Is located at the outer surface of the LDS material of the package to provide the metal pads at the outer surface of the package.
8. 8. The device of claim 7, comprising a metallization at the second side of the at least one semiconductor die, wherein the at least one metal via is coupled to the metallization.
9. 9. The device of claim 8, further comprising at least one metal via formed in the LDS material of the package between the outer surface of the package and the leadframe.
10. 10. The device of claim 9, further comprising a metal pillar electrically coupled to the first side of the at least one semiconductor die with the leadframe.
11. 11. The device of claim 7, further comprising a metal pillar electrically coupled to the first side of the at least one semiconductor die with the leadframe.
12. 12. The device of claim 7, further comprising at least one metal via in the LDS material of the package between the outer surface of the package and the leadframe.
13. 13. The device of claim 7, further comprising a metal pillar electrically coupling the first side of the at least one semiconductor die with the leadframe.
14. 14. The device of claim 7, further comprising at least one metal via in the LDS material of the package between the outer surface of the package and the leadframe.

Description

Method of manufacturing a semiconductor device and corresponding semiconductor device Priority statement The present application claims priority from italian patent application number 102020000031244 filed on 12/17 in 2020, the contents of which are incorporated herein by reference in their entirety to the maximum extent allowed by law. Technical Field The present invention relates to a semiconductor device. In particular, one or more embodiments may be applied to a semiconductor device such as an Integrated Circuit (IC). Background Semiconductor devices, such as flat leadless (QFN) packages, having peripheral pads at the bottom of the package to provide electrical connection via flip-chip mounting on a substrate, such as a Printed Circuit Board (PCB), have stimulated increasing interest in various applications. Good heat dissipation contributes to the adequate performance of these devices. To increase heat dissipation, exposed pads are now commonly used in standard QFN packages. However, it has been observed that this approach suffers from various reliability problems associated with power consumption. This is particularly true for flip-chip type semiconductor devices. There is a need in the art to help provide improved methods that overcome these disadvantages. Disclosure of Invention One or more embodiments may relate to a method. One or more embodiments may relate to a corresponding semiconductor device. One or more embodiments relate to molding a die and a leadframe in a device using a Laser Direct Structuring (LDS) material (e.g., a molding compound with a filler of chromia particles). One or more embodiments benefit from the proven ability of Laser Direct Structuring (LDS) technology to form vias and traces. One or more embodiments may exhibit detectable metal (e.g., copper) filled vias and heat dissipating molding compound (with chromia particles). One or more embodiments may facilitate high heat dissipation of a semiconductor device, possibly via double sided heat dissipation. One or more embodiments are compatible with those devices that benefit from good heat dissipation, such as in a flip-chip version. For example, this may be the case in power devices where fully exploiting package leads as input/output (I/O) nodes is a desirable feature, heat dissipation is primarily transferred (entrust) to the backside semiconductor material (silicon) through the top exposed pads. One or more embodiments benefit from a top thermal pad created by LDS activation and metal (e.g., cu) plating that provides improved heat dissipation compared to standard flip chip solutions. Drawings One or more embodiments will now be described, by way of example only, with reference to the accompanying drawings, in which: Fig. 1 is a sectional view of a semiconductor device according to an embodiment of the present specification; fig. 2 and 3 are cross-sectional views showing possible options for implementing embodiments of the present specification, and Fig. 4A-4G are illustrations of possible assembly flows that form embodiments of the present description. It should be appreciated that for clarity and ease of understanding, the drawings may not be drawn to the same scale. Detailed Description In the following description, numerous specific details are set forth in order to provide a thorough understanding of various examples of embodiments according to the description. Embodiments may be practiced without one or more of the specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the embodiments. Reference in the framework of this specification to "an embodiment" or "one embodiment" is intended to indicate that a particular configuration, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, phrases such as "in one embodiment" or the like that may occur throughout this specification are not necessarily referring to exactly one and the same embodiment. Furthermore, the particular structures, or characteristics may be combined in any suitable manner in one or more embodiments. Headings/references used herein are provided for convenience only and thus do not limit the scope of protection or the scope of the embodiments. Moreover, throughout the drawings, similar parts or elements are indicated with similar reference numerals unless the context indicates otherwise, and for brevity, a corresponding description will not be repeated for each drawing. Various types of conventional semiconductor devices include a leadframe on which one or more semiconductor chips or dies are mounted. The leadframe (or leadframe) is currently used to represent a metal frame that provides support for a semiconductor chip or die and electrical leads that couple the semiconductor chip or die to other electrical components or contacts. Basically, th