CN-114649338-B - Read-only memory

Abstract

Embodiments of the present disclosure relate to read only memory. The present description relates to a ROM comprising at least one first rewritable memory cell.

Inventors

• A. Mazaki
• M. Lisart
• B - vroemen.

Assignees

• 意法半导体(克洛尔2)公司
• 意法半导体(鲁塞)公司

Dates

Publication Date

20260508

Application Date

20211217

Priority Date

20201218

Claims (15)

1. 1. A memory, comprising: A first type of memory cell, the first type being an embedded intra-trench select memory type memory cell, and A second type of memory cells, each of the second type of memory cells comprising a transistor; wherein the first type of memory cell includes a first insulated gate and a second insulated gate stacked on each other, an Wherein the transistor of the second type of memory cell comprises a third insulated gate having a thickness equal to the sum of the thicknesses of the first and second insulated gates of the first type of memory cell.
2. 2. The memory of claim 1, wherein during operation the memory operates as a read only memory, wherein bits of a first state are defined by memory cells of the first type and bits of a second state are defined by memory cells of the second type.
3. 3. The memory of claim 1, wherein the transistor is a metal oxide semiconductor MOS transistor.
4. 4. The memory of claim 3 wherein the transistor is an N-channel MOS transistor.
5. 5. The memory of claim 1, wherein when a first threshold voltage of a transistor of the first type of memory cell is above a reference threshold voltage, then the transistor of the first type of memory cell represents a first bit value, and when the first threshold voltage of the transistor of the first type of memory cell is below the reference threshold voltage, then the transistor of the first type of memory cell represents a second bit value different from the first bit value.
6. 6. The memory of claim 1, wherein the first type of memory cell and the transistor comprise structures comprising, in order: a doped substrate of a first conductivity type; a first semiconductor layer of a second conductivity type on the doped substrate, and And a second semiconductor layer of the first conductivity type on the first semiconductor layer.
7. 7. The memory of claim 6, wherein the first and second insulated gates of the first type of memory cell are disposed on a first portion of a surface of the structure.
8. 8. A read only memory ROM comprising: a plurality of memory cells, each memory cell of the plurality of memory cells comprising: A field effect transistor for providing a reference threshold voltage, and A memory transistor having a first threshold voltage higher than the reference threshold voltage and a second threshold voltage lower than the reference threshold voltage, the memory cell storing a first bit value when the memory transistor has the first threshold voltage and storing a second bit value when the memory transistor has the second threshold voltage; Wherein the memory transistor includes a first insulated gate and a second insulated gate stacked on each other; Wherein the field effect transistor includes a third insulated gate having a thickness equal to a sum of thicknesses of the first and second insulated gates of the memory transistor.
9. 9. The ROM of claim 8, wherein the memory transistor is an embedded intra-trench select memory e-STM type, and wherein the field effect transistor is a metal oxide semiconductor MOS transistor.
10. 10. The read only memory ROM of claim 8 wherein said field effect transistor and said memory transistor comprise structures comprising, in order: a doped substrate of a first conductivity type; a first semiconductor layer of a second conductivity type on the doped substrate, and And a second semiconductor layer of the first conductivity type on the first semiconductor layer.
11. 11. The read only memory ROM of claim 10, wherein the first and second insulated gates of the memory transistor are disposed on a first portion of a surface of the structure.
12. 12. A method of manufacturing a read-only memory ROM, the read-only memory ROM comprising a plurality of memory cells, each memory cell of the plurality of memory cells comprising a first transistor and a second transistor that are rewritable, the method comprising: Sequentially depositing a first insulating layer and a first gate layer on the semiconductor structure; forming a cavity at a location of a gate of the second transistor in the first gate layer; sequentially depositing a second insulating layer and a second gate layer; Etching the first and second insulating layers and the second gate layer to enable formation of an insulated gate of the second transistor, and Etching the first and second insulating layers and the first and second gate layers to form a stack of two insulated gates of the first transistor, wherein the insulated gate of the second transistor has a thickness equal to a sum of thicknesses of the two insulated gates of the first transistor.
13. 13. The method of claim 12, wherein the structure comprises, in order: a second doped substrate of the first conductivity type; a third semiconductor layer of a second conductivity type on the second doped substrate, and And a fourth semiconductor layer of the first conductivity type on the third semiconductor layer.
14. 14. The method of claim 12, wherein the first transistor is of the e-STM type.
15. 15. The method of claim 12, wherein the semiconductor structure comprises at least one trench made of semiconductor material, and a location of a gate of the second transistor is laterally bounded on one side by the at least one trench.

Description

Read-only memory Cross Reference to Related Applications The application claims the benefit of french application number FR 2013741 filed on 18 of 12 months 2020, which is incorporated herein by reference. Technical Field The present disclosure relates generally to electronic systems and devices, and more particularly to memory circuits or memories. The present disclosure relates more particularly to Read Only Memory (ROM). Background Currently, miniaturization of electronic devices and improvement of their performance require improvement of data storage devices. In fact, the memory must be smaller and store more and more data. There are a number of different memory types. In fact, in some memories, stored data may be referred to and/or modified at any time, while other memories store data only when powered on. Flash memory is a volatile memory, i.e., memory that can write and/or modify data at any time. ROM is a non-rewritable memory into which data is typically written during manufacturing and can no longer be modified. The data stored in the ROM can only be referred to. It is desirable to at least partially improve certain aspects of known ROMs. Disclosure of Invention Smaller ROM is required. The ROM is required to be more resistant to hacking techniques such as reverse engineering. Embodiments overcome all or part of the disadvantages of known ROMs. Embodiments provide a ROM that includes at least one first rewritable memory cell. According to an embodiment, the first memory cell is of the e-STM type. According to one embodiment, the ROM further comprises at least one memory cell comprising a transistor. According to an embodiment, the transistor is a MOS transistor. According to an embodiment, the transistor is an N-channel MOS transistor. According to an embodiment, when the threshold voltage of the first memory cell or the second memory cell is higher than a threshold value, then the first memory cell or the second memory cell represents a first bit value, and when the threshold voltage is lower than the threshold value, then the first memory cell or the second memory cell represents a second bit value different from the first value. According to an embodiment, a first memory cell and a second memory cell comprise a structure comprising, in order, a doped substrate of a first conductivity type, a first semiconductor layer of a second conductivity type located on the substrate, and a second semiconductor layer of the first conductivity type located on the first semiconductor layer. According to an embodiment, a first memory cell includes a first insulated gate and a second insulated gate stacked on each other. According to an embodiment, the first and second insulated gates of the first memory cell are arranged on a first portion of the surface of the structure. According to an embodiment, the second memory cell comprises a third insulated gate having a thickness equal to the sum of the thicknesses of the first and second insulated gates of the first memory cell. Another embodiment provides a method of manufacturing a ROM comprising at least one third rewritable memory cell and at least one fourth memory cell, the memory cell comprising a transistor, the method comprising the successive steps of sequentially depositing a first insulating layer and a first gate layer on a semiconductor structure, forming a cavity at a gate location of the transistor of the fourth memory cell in the first gate layer, and sequentially depositing a second insulating layer and a second gate layer. According to one embodiment, the structure comprises, in order, a second doped substrate of a first conductivity type, a third semiconductor layer of the second conductivity type located on the substrate, and a third semiconductor layer of the first conductivity type located on the first semiconductor layer. According to one embodiment, the method further comprises the step of etching the first and second insulating layers and the step of etching the second gate layer capable of forming the insulating gate of the at least one second memory cell. According to an embodiment, the third rewritable memory cell is of the e-STM type. According to an embodiment, the method further comprises the step of etching the first and second insulating gate and the step of etching the first and second gate layers, enabling a stack of two insulating gates of a third memory cell of the e-STM type to be formed. According to an embodiment, the semiconductor structure comprises at least one trench made of semiconductor material, and the gate position of the transistor of the fourth memory cell is laterally delimited by the at least one trench on one side. Another embodiment provides a ROM comprising at least a first memory cell and a second memory cell of the e-STM type, each memory cell comprising a first insulated gate and a second insulated gate stacked on top of each other, wherein the first insulated gate is electrically coupled to the second insu