CN-114664340-B - Random seed generation circuit of memory system

Abstract

The application relates to a random seed generation circuit of a memory system. The random seed generation circuit includes a first address generation circuit, a second address generation circuit, a table circuit, and a seed generation circuit. The first address generation circuit generates an initial address based on the target page information. The second address generation circuit generates a plurality of table addresses based on the target page information and the plurality of partial addresses divided from the initial address. The table circuit outputs a plurality of table values corresponding to a plurality of table addresses, respectively, from the plurality of tables. The seed generation circuit generates a random seed based on the plurality of table values.

Inventors

• Cai Zhezhu

Assignees

• 爱思开海力士有限公司
• 爱思开海力士有限公司

Dates

Publication Date

20260421

Application Date

20210830

Priority Date

20201223

Claims (20)

1. 1. A random seed generation circuit of a memory system, the random seed generation circuit comprising: a first address generation circuit that generates an initial address based on target page information of a target page; A second address generating circuit that generates a plurality of table addresses based on the target page information and a plurality of partial addresses divided from the initial address; a table circuit for outputting a plurality of table values corresponding to the plurality of table addresses from a plurality of tables, respectively, and And a seed generation circuit for generating random seeds corresponding to the target page based on the table values.
2. 2. The random seed generation circuit of claim 1, wherein the target page information includes a word line index, a page level index, and an erase count corresponding to the target page.
3. 3. The random seed generation circuit of claim 2, wherein the first address generation circuit combines the word line index and the page level index to generate an index value, and performs an XOR operation on the index value and the erase count to generate the initial address.
4. 4. The random seed generation circuit of claim 1, Wherein the second address generation circuit includes a plurality of table address generation circuits, an Wherein each of the plurality of table address generating circuits generates a corresponding table address among the plurality of table addresses based on the target page information and the corresponding partial address among the plurality of partial addresses.
5. 5. The random seed generation circuit of claim 4, wherein each of the plurality of table address generation circuits comprises: A selection circuit for outputting a predetermined value from a plurality of predetermined values in response to the target page information, and And an XOR operator for performing an XOR operation on the predetermined value and the corresponding partial address to generate the corresponding table address.
6. 6. The random seed generation circuit of claim 5, wherein the plurality of predetermined values are different from each other.
7. 7. The random seed generation circuit of claim 1, wherein the seed generation circuit performs an addition operation on the plurality of table values and selects a plurality of bits at a plurality of predetermined positions within a result of the addition operation as the random seed.
8. 8. The random seed generation circuit of claim 1, wherein the seed generation circuit comprises: an adder circuit that performs addition operation on the plurality of table values and selects a plurality of bits at a plurality of predetermined positions within a result of the addition operation as an initial random seed, and A seed conversion circuit generates the random seed based on the initial random seed and a slice index.
9. 9. The random seed generation circuit of claim 8, wherein the seed conversion circuit comprises: A selection circuit for outputting a predetermined value from a plurality of predetermined values in response to the slice index, and An XOR operator performing an XOR operation on the predetermined value and the initial random seed to generate the random seed.
10. 10. A random seed generation circuit of a memory system, the random seed generation circuit comprising: A first address generation circuit that generates a plurality of partial addresses based on target page information of a target page; A second address generating circuit that selects a plurality of predetermined first values from a plurality of predetermined first value groups, respectively, based on the page level index, and converts the plurality of partial addresses into a plurality of table addresses, respectively, based on the plurality of predetermined first values; a table circuit for outputting a plurality of table values corresponding to the plurality of table addresses from a plurality of tables, respectively, and And a seed generation circuit for generating random seeds corresponding to the target page based on the table values.
11. 11. The random seed generation circuit of claim 10, Wherein the target page information includes a word line index corresponding to a target page, the page level index, and an erase count, and Wherein the first address generation circuit combines the word line index and the page level index to generate an index value, and performs an XOR operation on the index value and the erase count to generate an initial address, which is to be divided into the plurality of partial addresses.
12. 12. The random seed generation circuit of claim 10, Wherein the second address generating circuit includes a plurality of table address generating circuits that respectively receive the plurality of partial addresses to output the plurality of table addresses, and Wherein each of the plurality of table address generating circuits includes: A selection circuit receiving a respective predetermined first value set among the plurality of predetermined first value sets and outputting a predetermined first value from the respective predetermined first value set in response to the page level index, and And an XOR operator for performing an XOR operation on the predetermined first value and the corresponding partial address to generate a corresponding table address.
13. 13. The random seed generation circuit of claim 10, wherein the seed generation circuit comprises: an adder circuit that performs addition operation on the plurality of table values and selects a plurality of bits at a plurality of predetermined positions within a result of the addition operation as an initial random seed, and A seed conversion circuit generates the random seed based on the initial random seed and a slice index.
14. 14. The random seed generation circuit of claim 13, wherein the seed conversion circuit comprises: a selection circuit for outputting a predetermined second value from a plurality of predetermined second values in response to the slice index, and An XOR operator performing an XOR operation on the predetermined second value and the initial random seed to generate the random seed.
15. 15. A random seed generation circuit of a memory system, the random seed generation circuit comprising: An address generation circuit that generates a plurality of table addresses based on target page information of a target page; a table circuit for outputting a plurality of table values corresponding to the plurality of table addresses from a plurality of tables, respectively, and A seed generation circuit performs an addition operation on the plurality of table values, and generates a random seed corresponding to the target page based on a result of the addition operation.
16. 16. The random seed generation circuit of claim 15, wherein the address generation circuit comprises: A first address generation circuit for generating an initial address based on the target page information, and And a second address generating circuit that generates the plurality of table addresses based on the target page information and a plurality of partial addresses divided from the initial address.
17. 17. The random seed generation circuit of claim 16, Wherein the target page information includes a word line index, a page level index, and an erase count corresponding to the target page, and Wherein the first address generation circuit combines the word line index and the page level index to generate an index value, and performs an XOR operation on the index value and the erase count to generate the initial address.
18. 18. The random seed generation circuit of claim 16, Wherein the second address generation circuit includes a plurality of table address generation circuits, an Wherein each of the plurality of table address generating circuits generates a corresponding table address among the plurality of table addresses based on the target page information and the corresponding partial address among the plurality of partial addresses.
19. 19. The random seed generation circuit of claim 18, wherein each of the plurality of table address generation circuits comprises: A selection circuit for outputting a predetermined value from a plurality of predetermined values in response to the target page information, and And an XOR operator for performing an XOR operation on the predetermined value and the corresponding partial address to generate the corresponding table address.
20. 20. The random seed generation circuit of claim 15, wherein the seed generation circuit comprises: An adder circuit that performs the addition operation and selects a plurality of bits at a plurality of predetermined positions within a result of the addition operation as an initial random seed, and A seed conversion circuit generates the random seed based on the initial random seed and a slice index.

Description

Random seed generation circuit of memory system Cross Reference to Related Applications The present application claims priority from korean patent application No. 10-2020-0182543 filed on 12/23/2020, which is incorporated herein by reference in its entirety. Technical Field Various embodiments of the present disclosure relate generally to a random seed generation circuit, and more particularly, to a random seed generation circuit of a memory system. Background The memory system may be configured to store data provided from the host device in response to a write request from the host device. Moreover, the memory system may be configured to provide the stored data to the host device in response to a read request from the host device. The host device may be an electronic device capable of processing data, and may include a computer, a digital camera, a mobile phone, and the like. The memory system may become operational upon connection to the host device. The memory system may be manufactured to be embedded within the host device or to be detachable from the host device. When storing data of a particular pattern, the memory system may have a higher risk of errors occurring. Thus, a memory system may utilize a scheme in which data is randomized by a randomizer to store the randomized data. The performance of the randomizer, i.e., the degree to which data can be randomized, can affect the reliability of the memory system. Further, the complexity of the randomizer and memory usage may affect the performance of the memory system. Disclosure of Invention According to an embodiment of the present disclosure, a random seed generation circuit of a memory system may include a first address generation circuit, a second address generation circuit, a table circuit, and a seed generation circuit. The first address generation circuit may be configured to generate the initial address based on the target page information. The second address generation circuit may be configured to generate a plurality of table addresses based on the target page information and a plurality of partial addresses divided from the initial address. The table circuit may be configured to output a plurality of table values from the plurality of tables, the plurality of table values corresponding to the plurality of table addresses, respectively. The seed generation circuit may be configured to generate a random seed based on the plurality of table values. According to an embodiment of the present disclosure, a random seed generation circuit of a memory system may include a first address generation circuit, a second address generation circuit, a table circuit, and a seed generation circuit. The first address generation circuit may be configured to generate a plurality of partial addresses based on the target page information. The second address generation circuit may be configured to select a predetermined first value from the predetermined first value group, respectively, based on the page level index, and to convert the plurality of partial addresses to the plurality of table addresses, respectively, based on the predetermined first value. The table circuit may be configured to output a plurality of table values from the plurality of tables, the plurality of table values corresponding to the plurality of table addresses, respectively. The seed generation circuit may be configured to generate a random seed based on the plurality of table values. According to an embodiment of the present disclosure, a random seed generation circuit of a memory system may include an address generation circuit, a table circuit, and a seed generation circuit. The address generation circuit may be configured to generate a plurality of table addresses based on the target page information. The table circuit may be configured to output a plurality of table values from the plurality of tables, the plurality of table values corresponding to the plurality of table addresses, respectively. The seed generation circuit may be configured to perform an addition operation on the plurality of table values, and to generate a random seed based on a result of the addition operation. According to an embodiment of the present disclosure, an operation method of a controller may include generating a plurality of first data bars based on information of a storage unit, generating a plurality of second data bars based on the first data bars and first values, respectively, the first values being selected from first value groups according to the information, respectively, and the first values corresponding to the first data bars, respectively, selecting a plurality of second values from tables, each having second value entries corresponding to values that the corresponding second data bars may have, respectively, according to the values of the second data bars, respectively, generating random seeds based on the selected second values, randomizing data to be stored in the storage unit using the ran