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CN-114664345-B - SOT-MRAM memory cell, memory array, memory and operation method

CN114664345BCN 114664345 BCN114664345 BCN 114664345BCN-114664345-B

Abstract

The present disclosure provides an SOT-MRAM memory cell comprising a bottom electrode, a magnetic tunnel junction layer on the bottom electrode, a track Hall effect layer on the magnetic tunnel junction layer, a first transistor having a drain connected to the track Hall effect layer, and a second transistor having a drain connected to the bottom electrode. The disclosure also provides an SOT-MRAM memory, an operation method and an SOT-MRAM memory array.

Inventors

  • XING GUOZHONG
  • LIU LONG
  • ZHAO XUEFENG
  • WANG DI
  • LIN HUAI
  • ZHANG HAO
  • Wang Ziwai

Assignees

  • 中国科学院微电子研究所

Dates

Publication Date
20260512
Application Date
20220302

Claims (14)

  1. 1. An SOT-MRAM memory cell, comprising: A bottom electrode; a magnetic tunnel junction layer on the bottom electrode; A track hall effect layer on the magnetic tunnel junction layer; A heavy metal layer between the magnetic tunnel junction layer and the track hall effect layer; A first transistor having a drain connected to the track Hall effect layer, and A second transistor having a drain connected to the bottom electrode; The track Hall effect layer is used for converting the write current into track polarized track current through the track Hall effect, the heavy metal layer is used for converting the write current into spin polarized spin current through spin track coupling, the track current diffused into the heavy metal layer is converted into self-rotational flow under the strong spin track coupling effect of the heavy metal layer, the self-rotational flow generated by the heavy metal layer and the spin current formed by the track current conversion are opposite in polarity, and competition self-rotational flow is formed and used for achieving deterministic magnetization inversion without external magnetic field assistance.
  2. 2. The SOT-MRAM memory cell of claim 1, wherein the magnetic tunnel junction layer comprises a bottom-up ferromagnetic reference layer, a nonmagnetic barrier layer, and a ferromagnetic free layer.
  3. 3. The SOT-MRAM memory cell of claim 2, wherein the ferromagnetic reference layer is a pinned structure comprising a bottom-up antiferromagnetic structure layer, a second spacer layer, and a reference layer.
  4. 4. The SOT-MRAM memory cell of claim 3, wherein the antiferromagnetic structure layer has a RKKY effect and comprises a bottom-up second ferromagnetic layer, a first spatial layer, and a first ferromagnetic layer, the first spatial layer being configured to form an antiferromagnetic coupling between the first ferromagnetic layer and the second ferromagnetic layer.
  5. 5. The SOT-MRAM memory cell of claim 4, wherein the first ferromagnetic layer and the second ferromagnetic layer are structured as periodic synthetic ferromagnetic structures of Co/Pt or Co/Pd.
  6. 6. The SOT-MRAM memory cell of claim 1, further comprising: a source line and a bit line, wherein, The source line is connected with the track Hall effect layer; the bit line is connected with the sources of the first transistor and the second transistor respectively.
  7. 7. The SOT-MRAM memory cell of claim 1, wherein the heavy metal layer is one or more of Pt, ta, W, and Gd.
  8. 8. The SOT-MRAM memory cell of claim 2, wherein the ferromagnetic reference layer is any one of Co, coFeB, co/Pt and comprises a synthetic antiferromagnetic structure; The bottom electrode is made of one or more materials of Pt, ta and W; the nonmagnetic barrier layer is composed of MgO or Al 2 O 3 ; the ferromagnetic free layer is any one of Co, coFe and CoFeB; the track hall effect layer is composed of Cu or Cr.
  9. 9. A SOT-MRAM memory according to claim 1, comprising SOT-MRAM memory cells.
  10. 10. A method of operating a SOT-MRAM memory as in claim 9, comprising: And controlling voltage bias applied to the first transistor and the second transistor in the SOT-MRAM memory, and respectively performing data writing and reading operation on the SOT-MRAM memory.
  11. 11. The method of claim 10, wherein performing a data read operation on the SOT-MRAM memory comprises: And controlling the first transistor to be turned off and the second transistor to be turned on, and reading the stored data in the SOT-MRAM through a tunnel magneto-resistance effect.
  12. 12. The method of claim 10, wherein the performing a data write operation to the SOT-MRAM memory comprises: And controlling the first transistor to be turned on and the second transistor to be turned off, and forming competing spin flow through the track Hall effect and the spin Hall effect to realize data writing of the SOT-MRAM.
  13. 13. An SOT-MRAM memory array, comprising: The plurality of SOT-MRAM memory cells of any one of claims 1 to 8, wherein each SOT-MRAM memory cell is arranged periodically.
  14. 14. The SOT-MRAM memory of claim 13, comprising a SOT-MRAM memory array.

Description

SOT-MRAM memory cell, memory array, memory and operation method Technical Field The present disclosure relates to the field of magnetic random access memory technology, and in particular, to an SOT-MRAM memory cell, a memory array, a memory, and a method of operation. Background SOT-MRAM (Spin-Orbit Torque Magnetic Random Access Memory, spin-orbit torque magnetic memory) is used as a new generation magnetic random access memory, and is expected to become a next generation general nonvolatile memory because of the characteristics of subnanosecond writing speed, high data retention time, high durability, low power consumption, radiation resistance and the like, and the unique three-terminal device structure with separate reading and writing overcomes the bottleneck problems of information writing speed and reliability existing in the previous generation STT-MRAM. However, the technical challenges of SOT-MRAM, which have not been completely overcome yet, are that for SOT-MRAM with perpendicular anisotropy (PMA) the data writing requires the addition of an in-plane magnetic field along the current direction, limiting the integration, miniaturization and large-scale application of SOT-MRAM. The existing data writing method without external magnetic field assistance, such as structure asymmetry, exchange bias/interlayer exchange coupling introduction of built-in-plane field, and the like, has the problems of difficult micro integration and poor compatibility with CMOS technology. Meanwhile, the SOT-MRAM in the prior art uses a large amount of expensive heavy metal materials as the spin-orbit coupling layer, which is not beneficial to further reducing the cost of the SOT-MRAM. Disclosure of Invention In view of the foregoing, the present disclosure provides an SOT-MRAM memory cell, memory array, memory and method of operation that aims to implement SOT-MRAM memory cells without the assistance of an externally applied magnetic field in combination with the orbital Hall effect, the spin-orbit precession effect of ferromagnetic materials, or the planar Hall effect, competing spin flows. A first aspect of the present disclosure provides an SOT-MRAM memory cell comprising a bottom electrode, a magnetic tunnel junction layer on the bottom electrode, a track Hall effect layer on the magnetic tunnel junction layer, a first transistor having a drain connected to the track Hall effect layer, and a second transistor having a drain connected to the bottom electrode. Further, the memory cell further includes a heavy metal layer between the magnetic tunnel junction layer and the track Hall effect layer. Further, the track hall effect layer and the heavy metal layer are configured to pass a write current, wherein the track hall effect layer is configured to convert the write current into a track-polarized orbital flow by the track hall effect, and the heavy metal layer is configured to convert the write current into a spin-polarized spin flow by spin-orbit coupling. Further, the orbital flow diffused into the heavy metal layer is converted into a self-rotational flow under the strong spin-orbit coupling action of the heavy metal layer. Further, the self-rotational flow generated by the heavy metal layer and the self-rotational flow formed by the orbital flow are opposite in polarity, so that competing self-rotational flow is formed, and the competing self-rotational flow is used for realizing the deterministic magnetization inversion assisted by an externally applied magnetic field. Further, the magnetic tunnel junction layer includes a bottom-up ferromagnetic reference layer, a nonmagnetic barrier layer, and a ferromagnetic free layer. Further, the ferromagnetic reference layer adopts a pinning structure, and comprises an antiferromagnetic structure layer, a second space layer and a reference layer from bottom to top. Further, the antiferromagnetic structure layer has RKKY effect and comprises a second ferromagnetic layer, a first space layer and a first ferromagnetic layer from bottom to top, wherein the first space layer is used for forming antiferromagnetic coupling between the first ferromagnetic layer and the second ferromagnetic layer. Further, the first ferromagnetic layer and the second ferromagnetic layer form a periodic composite ferromagnetic structure of Co/Pt or Co/Pd. Further, the semiconductor device further comprises a source line and a bit line, wherein the source line is connected with the track Hall effect layer, and the bit line is connected with the sources of the first transistor and the second transistor respectively. Further, the heavy metal layer is one or more of Pt, ta, W and Gd. Further, the ferromagnetic reference layer is Co, coFeB, co/Pt and comprises any one of synthetic antiferromagnetic structures, the bottom electrode is made of one or more materials of Pt, ta and W, the nonmagnetic barrier layer is made of MgO or Al 2O3, the ferromagnetic free layer is any one of Co, coFe and CoFeB, and the t