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CN-114664662-B - Semiconductor structure and forming method thereof

CN114664662BCN 114664662 BCN114664662 BCN 114664662BCN-114664662-B

Abstract

The embodiment of the invention provides a semiconductor structure and a forming method thereof, wherein an initial substrate is provided, the surface of the initial substrate comprises a well region and a drift region which are adjacent, the well region and a partial region which faces the well region with the drift region are taken as fin regions, the partial region which faces away from the well region of the drift region is taken as a platform region, the initial substrate with partial thickness of the partial region is removed in the fin regions, a substrate, a fin portion and a platform which is adjacent to the fin portion are formed, the initial substrate with the residual thickness is taken as the substrate, the initial substrate which protrudes from the substrate in the fin region is taken as the fin portion, the initial substrate which protrudes from the substrate in the platform region is taken as the platform, a grid structure which spans across the fin portion is formed, the grid structure covers partial drift region and partial well region, a source electrode is formed in the well region, and a drain electrode is formed in the drift region. The embodiment of the invention can improve the electrical performance of the semiconductor structure.

Inventors

  • ZHAO HAI
  • ZHANG JINSHU

Assignees

  • 中芯国际集成电路制造(上海)有限公司
  • 中芯国际集成电路制造(北京)有限公司

Dates

Publication Date
20260505
Application Date
20201223

Claims (11)

  1. 1. A method of forming a semiconductor structure, comprising: Providing an initial substrate, wherein the surface of the initial substrate comprises a well region and a drift region which are adjacent, the well region and a partial region of the drift region facing the well region are taken as fin regions, and a partial region of the drift region facing away from the well region is taken as a platform region; removing an initial substrate with partial thickness of a partial region in the fin region to form a substrate, a fin portion and a platform adjacent to the fin portion, wherein the initial substrate with the residual thickness is taken as the substrate, the initial substrate protruding out of the substrate in the fin region is taken as the fin portion, and the initial substrate protruding out of the substrate in the platform region is taken as the platform; Forming a gate structure crossing the fin part, wherein the gate structure covers part of the drift region and part of the well region, and the gate structure is adjacent to the platform or the distance between the gate structure and the platform is less than or equal to 10 nm-200 nm; forming a barrier layer on one side of the gate structure, which faces the platform, and covering at least part of the drift region, wherein the barrier layer is a metallization barrier layer and is used for preventing doped ions in the drift region from diffusing outwards; and forming a source electrode in the well region and forming a drain electrode in the drift region.
  2. 2. The method of claim 1, wherein removing a portion of the thickness of the initial substrate of the partial region within the fin region comprises: Forming a patterned first mask layer on the initial substrate, wherein the first mask layer exposes the fin region and part of the initial substrate of the platform region; Forming a patterned second mask layer on the first mask layer, wherein the second mask layer covers the first mask layer of the platform region and exposes the first mask layer of the fin region; And etching to remove the initial substrate with partial thickness by taking the first mask layer and the second mask layer as masks, and forming a substrate and a fin part protruding out of the substrate in the fin part region.
  3. 3. The method of claim 2, wherein in the step of removing the partial thickness of the initial substrate in the fin region, the etching further comprises, after removing the partial thickness of the initial substrate: Removing the second mask layer; Forming a sacrificial layer on one side of the substrate with the fin part, wherein the sacrificial layer covers the substrate, the fin part and the first mask layer; removing part of the thickness of the sacrificial layer until part of the first mask layer is exposed; etching to remove the first mask layer; And removing the sacrificial layer after etching to remove the first mask layer.
  4. 4. The method of claim 3, wherein the sacrificial layer is a spin-on carbon layer or an organic dielectric layer.
  5. 5. The method of claim 1, wherein the fin region comprises an isolation region on a side of the fin region facing away from the mesa region, the isolation region further comprising, prior to forming a gate structure across the fin after removing a portion of a thickness of an initial substrate of a portion of the region within the fin region: removing the fin parts in the isolation region to form an isolation trench; And forming an isolation material layer covering the substrate in the fin part region, wherein the isolation material layer in the isolation region is used as an isolation structure, and the isolation material layer between the fin parts is used as an isolation layer.
  6. 6. The method of forming a semiconductor structure of claim 5, wherein: in the step of forming the fin portion, a plurality of pseudo fin portions parallel to the fin portion are also formed; and in the step of removing the fin parts with at least partial height in the isolation region, the pseudo fin parts are also removed.
  7. 7. The method of forming a semiconductor structure of claim 1, wherein the gate structure comprises a gate dielectric layer, a gate and a sidewall, the forming a gate structure across the fin comprising: forming a gate dielectric material layer which covers one side of the initial substrate, which is provided with the fin part, in a conformal manner; forming a grid electrode crossing the fin part on the grid dielectric material layer, wherein the grid electrode covers part of the side wall and part of the top of the fin part; forming side walls on two sides of the grid electrode; and removing the exposed gate dielectric material layer by taking the grid electrode and the side wall as masks, and taking the residual gate dielectric material layer as a gate dielectric layer.
  8. 8. The method of forming a semiconductor structure of claim 7, wherein the forming a gate across the fin on the gate dielectric layer comprises: forming a gate material layer covering one side of the substrate with the fin part; Patterning the gate material layer to form a gate and a plurality of dummy gates in parallel with the gate; And removing the dummy gate and the side walls at two sides of the dummy gate after the side walls are formed at two sides of the gate.
  9. 9. A semiconductor structure, comprising: the surface of the substrate comprises a well region and a drift region which are adjacent, wherein the well region and a partial region of the drift region facing the well region are fin regions, and a partial region of the drift region facing away from the well region is a platform region; the fin part is positioned in the fin part area and protrudes out of the substrate, the fin part is positioned in the platform area and protrudes out of the platform of the substrate, and the fin part is adjacent to the platform; the platform, the fin part and the substrate are obtained by etching the same semiconductor material layer, and the platform is used for partial pressure; The grid structure stretches across the fin part and covers part of the drift region and part of the well region, and the grid structure is adjacent to the platform or the distance between the grid structure and the platform is smaller than or equal to 10-200 nm; A source electrode located in the well region and a drain electrode located in the drift region; the semiconductor device further comprises a blocking layer which is positioned on one side of the grid structure facing the platform and covers at least part of the drift region.
  10. 10. The semiconductor structure of claim 9, further comprising a device region and an isolation region, wherein the device region is adjacent to the mesa region, the isolation region is located on a side of the device region away from the mesa region, an isolation trench having a bottom lower than a top of the fin is disposed in the isolation region, an isolation structure is disposed in the isolation trench, and an isolation layer exposing a portion of a height of the fin is disposed in the device region.
  11. 11. The semiconductor structure of claim 9, further comprising a gate dielectric layer, a gate and a sidewall, wherein the sidewall is located on two sides of the gate, and the gate dielectric layer is located between the fin and the gate.

Description

Semiconductor structure and forming method thereof Technical Field Embodiments of the present disclosure relate to semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same. Background Semiconductor devices are electronic devices that have electrical conductivity between good electrical conductors and insulators, and that utilize the specific electrical characteristics of semiconductor materials to perform specific functions, and can be used to generate, control, receive, transform, amplify signals, and perform energy conversion. The conventional semiconductor devices include field effect transistors, bipolar transistors, transistor diodes, and the like. Among them, in particular, laterally diffused metal oxide semiconductor (LATERALLY DIFFUSED METAL OXIDE SEMICONDUCTOR, LDMOS) is widely used in power integrated circuits because it is more compatible with the logic process of complementary metal oxide semiconductor (Complementary Metal Oxide Semiconductors, CMOS). In semiconductor manufacturing, with the trend of very large scale integrated circuits, the feature size of integrated circuits is continuously reduced, and in order to adapt to smaller feature sizes, the channel length of transistors is also continuously shortened. However, as the channel length of the device is shortened, the distance between the source and the drain of the device is also shortened, so that the control capability of the gate structure on the channel is further and further reduced, and the difficulty of pinching off the channel by the gate voltage is further and further increased, so that the phenomenon of subthreshold leakage (subthreshold leakage), namely the so-called short channel effect (SCE: short-CHANNEL EFFECTS), is more likely to occur. Therefore, in order to better adapt to the reduction of the feature size, the semiconductor process gradually starts to transition from a planar transistor to a three-dimensional transistor with higher efficiency, such as an LDMOS fin field effect transistor, in the device structure, a gate structure can control an ultrathin body (fin portion) from at least two sides, compared with the planar LDMOS, the gate structure has stronger control capability on a channel, can well inhibit a short channel effect, and has better compatibility with the existing integrated circuit manufacturing compared with other devices. The electrical performance of the semiconductor devices formed by the prior art is still to be improved. Disclosure of Invention The problem to be solved by the present invention is how to provide a semiconductor structure and a method for forming the same, which can improve the electrical performance of the device. In order to solve the above problems, the present invention provides a method for forming a semiconductor structure, including: Providing an initial substrate, wherein the surface of the initial substrate comprises a well region and a drift region which are adjacent, the well region and a partial region of the drift region facing the well region are taken as fin regions, and a partial region of the drift region facing away from the well region is taken as a platform region; Removing an initial substrate with partial thickness of a partial region in the fin region to form a substrate, a fin and a platform adjacent to the fin region, wherein the initial substrate with the residual thickness is taken as the substrate, the initial substrate protruding out of the substrate in the fin region is taken as the fin region, and the initial substrate protruding out of the substrate in the platform region is taken as the platform; Forming a gate structure crossing the fin part, wherein the gate structure covers part of the drift region and part of the well region; and forming a source electrode in the well region and forming a drain electrode in the drift region. Correspondingly, the invention also provides a semiconductor structure, which comprises: the surface of the substrate comprises a well region and a drift region which are adjacent, wherein the well region and a partial region of the drift region facing the well region are fin regions, and a partial region of the drift region facing away from the well region is a platform region; The fin part is positioned in the fin part area and protrudes out of the substrate, the fin part is positioned in the platform area and protrudes out of the platform of the substrate, and the fin part is adjacent to the platform; a gate structure crossing the fin, the gate structure covering a portion of the drift region and a portion of the well region; a source located within the well region, and a drain located within the drift region. Compared with the prior art, when the fin part is formed, the embodiment of the invention is also provided with the platform adjacent to the fin part and the drift region at least comprising the platform, so that when the drain electrode in the embodiment of t