CN-114664795-B - Multi-chip system and operating method thereof

CN114664795BCN 114664795 BCN114664795 BCN 114664795BCN-114664795-B

Abstract

The invention provides a multi-chip system and an operation method of the multi-chip system. The multi-chip system includes a first chip and a second chip. The first chip and at least one second chip are arranged on the circuit layer. The first chip comprises a first selection pin and a first test circuit. The first selection pin receives a first selection signal. The first test circuit is coupled to the first selection pin and includes a plurality of first input/output pins. Each second chip comprises a second selection pin and a second test circuit. The second selection pin receives a second selection signal. The second test circuit is coupled to the second selection pin and includes a plurality of second input/output pins. The first input/output pins are correspondingly connected with the second input/output pins of each second chip and are connected to the common wirings. The multi-chip system and the operation method of the multi-chip system can effectively save the number of solder balls and provide good testability design test function.

Inventors

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Assignees

上海壁仞智能科技有限公司

Dates

Publication Date: 20260505
Application Date: 20220302

Claims (9)

1. A multi-chip system, comprising: The first chip, set up on the circuit layer, include: A first selection pin for receiving the first selection signal, and A first test circuit coupled to the first selection pins and including a plurality of first input/output pins, and A plurality of second chips disposed on the circuit layer, each of the second chips including: A second selection pin for receiving a second selection signal, and The second test circuit is coupled to the second selection pin and comprises a plurality of second input/output pins, Wherein the plurality of first input/output pins are correspondingly connected with the plurality of second input/output pins of each second chip and are connected to a plurality of common wires in the circuit layer or the substrate, and each common wire in the plurality of common wires is connected to a solder ball positioned between the circuit layer and the substrate, Wherein the first test circuit comprises: The first test units respectively correspond to the first input/output pins, and each first test unit comprises a first output enabling end, a first data output end, a first data input end and one of the first input/output pins; A first AND gate unit, wherein a first input terminal of the first AND gate unit receives the first selection signal, a second input terminal of the first AND gate unit receives a first test control signal, and output terminals of the first AND gate unit are respectively coupled to the first output enable terminals of the plurality of first test units, and A first internal operation test unit, wherein the first internal operation test unit provides first output data to the first data output terminal when the first output enable terminal of the first test unit is enabled, receives first input data from the first data input terminal when the first output enable terminal of the first test unit is disabled, and tests the first input data, Wherein the second test circuit includes: the second test units respectively correspond to the second input/output pins, and each second test unit comprises a second output enabling end, a second data output end, a second data input end and one of the second input/output pins; a second AND gate unit, wherein a first input terminal of the second AND gate unit receives the second selection signal, a second input terminal of the second AND gate unit receives a second test control signal, and output terminals of the second AND gate unit are respectively coupled with the second output enable terminals of the second test units, and And a second internal operation test unit, wherein the second internal operation test unit provides second output data to the second data output terminal when the second output enable terminal of the second test unit is enabled, and receives second input data from the second data input terminal and tests the second input data when the second output enable terminal of the second test unit is disabled.
2. The multi-chip system of claim 1, wherein the circuit layer is disposed on the substrate by a plurality of first solder balls, the plurality of first input-output pins and the plurality of second input-output pins of each of the second chips are connected in the circuit layer, and the plurality of common traces, the first select pins and the second select pins of each of the second chips are respectively connected to the plurality of first solder balls.
3. The multi-chip system of claim 1, wherein the circuit layer is disposed on a substrate by a plurality of first solder balls, a plurality of second solder balls opposite to the plurality of first solder balls are further disposed on the substrate, the plurality of first input output pins and the plurality of second input output pins of each of the second chips are connected in the substrate, and the plurality of common traces, the first select pins and the second select pins of each of the second chips are respectively connected with the plurality of second solder balls.
4. The multi-chip system of claim 1, wherein when the first chip is operated in a test mode according to the first selection signal and each of the second chips is operated in a high-impedance mode according to the second selection signal, the first chip obtains first input data of the first chip or transmits first output data of the first chip through the plurality of first input-output pins and the plurality of common traces.
5. The multi-chip system of claim 4, wherein the first test unit receives the first output data from the data output and outputs the first output data from one of the plurality of first input output pins when the output enable of the first test unit is enabled, When the output enable terminal of the first test unit is disabled, the first test unit receives the first input data from one of the plurality of first input output pins and outputs the first input data from the first data input terminal.
6. The multi-chip system of claim 1, wherein when the first chip is operated in a high-impedance mode according to the first selection signal and one of the plurality of second chips is operated in a test mode according to the second selection signal of the second chip under test, and a non-second chip other than the second chip under test is operated in the high-impedance mode according to the second selection signal of the non-second chip under test, the second chip under test obtains second input data of the second chip under test or transmits second output data of the second chip under test through the plurality of second input/output pins and the plurality of common traces.
7. The multi-chip system of claim 6, wherein the second test unit receives the second output data from the data output and outputs the second output data from one of the plurality of second input output pins when the output enable of the second test unit is enabled, When the output enable terminal of the second test unit is disabled, the second test unit receives the second input data from one of the plurality of second input output pins and outputs the second input data from the second data input terminal.
8. The multi-chip system of claim 1, wherein the first chip and the plurality of second chips are disposed side-by-side on the wiring layer.
9. A method of operating a multi-chip system, the multi-chip system comprising a first chip and a plurality of second chips, the first chip comprising a first select pin and a first test circuit, the first test circuit being coupled to the first select pin, the first test circuit comprising a plurality of first input output pins, each of the second chips comprising a second select pin and a second test circuit, the second test circuit being coupled to the second select pin, the second test circuit comprising a plurality of second input output pins, the first chip and the plurality of second chips being disposed on a wiring layer, the plurality of first input output pins being correspondingly connected to the plurality of second input output pins of each of the second chips and being connected to a plurality of common traces in the wiring layer or substrate, and each of the plurality of common traces being connected to solder balls located between the wiring layer and the substrate, Wherein, the operation method comprises the following steps: receiving a first selection signal through the first selection pin and a second selection signal through the second selection pin; When the first chip is operated in a test mode according to the first selection signal and each of the second chips is operated in a high-resistance mode according to the second selection signal, acquiring first input data of the first chip or transmitting first output data of the first chip through the plurality of first input/output pins and the plurality of common wirings, and When the first chip operates in the high-resistance mode according to the first selection signal, and one second chip to be tested in the plurality of second chips operates in the test mode according to the second selection signal of the second chip to be tested, and simultaneously a second chip not to be tested in the plurality of second chips operates in the high-resistance mode according to the second selection signal of the second chip not to be tested, second input data of the second chip to be tested or second output data of the second chip to be tested are obtained through the plurality of second input/output pins and the plurality of common wirings, Wherein the first test circuit comprises: The first test units respectively correspond to the first input/output pins, and each first test unit comprises a first output enabling end, a first data output end, a first data input end and one of the first input/output pins; A first AND gate unit, wherein a first input terminal of the first AND gate unit receives the first selection signal, a second input terminal of the first AND gate unit receives a first test control signal, and output terminals of the first AND gate unit are respectively coupled to the first output enable terminals of the plurality of first test units, and A first internal operation test unit, wherein the first internal operation test unit provides first output data to the first data output terminal when the first output enable terminal of the first test unit is enabled, receives first input data from the first data input terminal when the first output enable terminal of the first test unit is disabled, and tests the first input data, Wherein the second test circuit includes: the second test units respectively correspond to the second input/output pins, and each second test unit comprises a second output enabling end, a second data output end, a second data input end and one of the second input/output pins; a second AND gate unit, wherein a first input terminal of the second AND gate unit receives the second selection signal, a second input terminal of the second AND gate unit receives a second test control signal, and output terminals of the second AND gate unit are respectively coupled with the second output enable terminals of the second test units, and And a second internal operation test unit, wherein the second internal operation test unit provides second output data to the second data output terminal when the second output enable terminal of the second test unit is enabled, and receives second input data from the second data input terminal and tests the second input data when the second output enable terminal of the second test unit is disabled.

Description

Multi-chip system and operating method thereof Technical Field The present invention relates to integrated systems, and more particularly to a multichip system and a method of operating a multichip system. Background In response to the design for testability (Design for Testability, DFT) requirements in the fabrication of high-speed chips, each chip in the multi-chip system currently requires a corresponding test circuit and a plurality of input/output pins for use in the design for testability test function. Therefore, the integrated volume of the multi-chip system is affected by a large number of solder balls for connection with a plurality of input-output pins, so that an excessive area of the circuit board is occupied, and the volume of the multi-chip system cannot be miniaturized. Disclosure of Invention The invention is directed to a multi-chip system and a method of operating a multi-chip system that can effectively save the number of solder balls and embody good testability design (Design for testing, DFT) test functions. According to an embodiment of the present invention, the multi-chip system of the present invention includes a first chip and at least one second chip. The first chip is arranged on the circuit layer. The first chip comprises a first selection pin and a first test circuit. The first selection pin receives a first selection signal. The first test circuit is coupled to the first selection pin and includes a plurality of first input/output pins. At least one second chip is disposed on the wiring layer. Each second chip comprises a second selection pin and a second test circuit. The second selection pin receives a second selection signal. The second test circuit is coupled to the second selection pin and includes a plurality of second input/output pins. The first input/output pins are correspondingly connected with the second input/output pins and are connected to the common wirings. According to an embodiment of the present invention, the method of operating a multichip system of the present invention is applicable to multichip systems. The multi-chip system includes a first chip and at least one second chip. The first chip comprises a first selection pin and a first test circuit. The first test circuit is coupled to the first selection pin. The first test circuit comprises a plurality of first input/output pins. Each second chip comprises a second selection pin and a second test circuit. The second test circuit is coupled to the second selection pin. The second test circuit comprises a plurality of second input/output pins. The first chip and at least one second chip are arranged on the circuit layer. The first input/output pins are correspondingly connected with the second input/output pins of each second chip and are connected to the common wirings. The operation method comprises the steps of receiving a first selection signal through a first selection pin, receiving a second selection signal through a second selection pin, obtaining first input data of the first chip or sending first output data of the first chip through a plurality of first input/output pins and a plurality of common wirings when the first chip is operated in a test mode according to the first selection signal and each second chip is operated in a high-resistance mode according to the second selection signal, and obtaining second input data of the second chip or sending second output data of the second chip through a plurality of second input/output pins and a plurality of common wirings when the first chip is operated in a high-resistance mode according to the first selection signal and one second chip to be tested in the test mode according to the second selection signal and simultaneously non-second chips outside the at least one second chip are operated in the high-resistance mode according to the second selection signal of the non-second chip to be tested. Based on the above, the multi-chip system and the operation method of the multi-chip system of the present invention can realize the characteristic of common wiring through the design and the coupling mode of the test circuits in each chip, and can effectively save the number of solder balls (can effectively save the volume of the multi-chip system) and can embody a good testability design test function. In order to make the above features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below. Drawings FIG. 1 is a schematic circuit diagram of a multi-chip system according to an embodiment of the invention; FIG. 2A is a flow chart of a method of operation of a multichip system according to an embodiment of the invention; FIG. 2B is a schematic circuit diagram of a test unit according to an embodiment of the invention; FIG. 3 is a schematic diagram of a multi-chip system according to an embodiment of the invention; fig. 4 is a schematic diagram of a multi-chip system according to anoth