CN-114664863-B - Silicon-on-insulator chip structure with substrate embedded optical waveguide and method

Abstract

A silicon-on-insulator (SOI) chip structure and method having a substrate embedded in an optical waveguide is disclosed. In the method, an optical waveguide is formed within a trench in a bulk substrate prior to a wafer bonding process to form an SOI structure. Subsequently, a front end of line (FEOL) process may be performed to form additional optical and/or electronic devices in and/or over the silicon layer. By embedding the optical waveguide in the substrate prior to wafer bonding rather than forming it during the FEOL process, severe limitations on the size of the core layer of the optical waveguide are avoided. The core layer of the substrate embedded in the optical waveguide may be relatively large so that the cut-off wavelength may be relatively long. Thus, such substrate embedded optical waveguides provide different functionality to SOI chip structures than FEOL optical waveguides.

Inventors

• HOLT JUDSON R
• BIAN YUSHENG
• SHAO DALI

Assignees

• 格芯(美国)集成电路科技有限公司
• 格芯(美国)集成电路科技有限公司

Dates

Publication Date

20260421

Application Date

20211123

Priority Date

20201223

Claims (19)

1. 1. A silicon-on-insulator chip structure comprising: a substrate; a first waveguide located in a trench of the substrate, wherein the first waveguide comprises: A cladding layer lining the trench, wherein the cladding layer has a horizontal portion located above and immediately adjacent to the bottom of the trench and a vertical portion located laterally immediately adjacent to the sidewall of the trench and further extending vertically from the horizontal portion to the top of the trench, and A core layer on the cladding layer, wherein the core layer is located above and immediately adjacent to the horizontal portions, extends laterally between and immediately adjacent to the vertical portions, and further extends vertically from the horizontal portions to the top of the trench; An insulating layer over and adjacent to the substrate and extending further laterally to at least the vertical portion of the cladding layer at the top of the trench, and And a silicon layer over and adjacent to the insulating layer.
2. 2. The silicon-on-insulator chip structure of claim 1, Wherein the substrate comprises silicon, Wherein the cladding layer of the first waveguide comprises an oxide cladding layer, and Wherein the core layer of the first waveguide includes any one of a silicon nitride core layer and an oxide core layer different from the oxide cladding layer.
3. 3. The silicon-on-insulator chip structure of claim 1 wherein the cladding layer comprises a multi-layer cladding layer having a lower cladding layer and an upper cladding layer, the lower cladding layer comprising the horizontal portion and being on the bottom of the trench, the upper cladding layer comprising the vertical portion and being above the lower cladding layer and laterally abutting the sidewall of the trench.
4. 4. The silicon-on-insulator chip structure of claim 1, further comprising: An insulating region in the silicon layer above the first waveguide, and At least one second waveguide is located over the insulating region.
5. 5. The silicon-on-insulator chip structure of claim 4, wherein the core layer of the second waveguide covers the core layer of the first waveguide.
6. 6. The silicon-on-insulator chip structure of claim 5, further comprising a waveguide extension extending through the insulating region and the insulating layer, wherein the core layer of the first waveguide and the core layer of the second waveguide are in contact with the waveguide extension.
7. 7. The silicon-on-insulator chip structure of claim 4, wherein the core layer of the second waveguide is completely offset from the core layer of the first waveguide.
8. 8. The silicon-on-insulator chip structure of claim 4, wherein a size of the core layer of the second waveguide is smaller than a size of the core layer of the first waveguide.
9. 9. The silicon-on-insulator chip structure of claim 4, further comprising a third waveguide, wherein the core layer of the third waveguide comprises a portion of the silicon layer.
10. 10. The silicon-on-insulator chip structure of claim 1 further comprising additional optics comprising a portion of the silicon layer.
11. 11. The silicon-on-insulator chip structure of claim 1 further comprising an electronic device comprising a portion of the silicon layer.
12. 12. The silicon-on-insulator chip structure of claim 1, Wherein the substrate is provided with an additional groove, Wherein the structure further comprises an insulating region in the additional trench, and Wherein the insulating layer also extends laterally over the insulating region.
13. 13. A method of forming a silicon-on-insulator chip structure, the method comprising: Providing a substrate; Forming a trench in the substrate; Forming a first waveguide in the trench, wherein the first waveguide comprises: A cladding layer lining the trench, wherein the cladding layer has a horizontal portion located above and immediately adjacent to the bottom of the trench and a vertical portion located laterally immediately adjacent to the sidewall of the trench and further extending vertically from the horizontal portion to the top of the trench, and A core layer on the cladding layer, wherein the core layer is located above and immediately adjacent to the horizontal portions, extends laterally between and immediately adjacent to the vertical portions, and further extends vertically from the horizontal portions to the top of the trench; Forming an insulating layer over and immediately adjacent to the substrate and extending further laterally over at least the vertical portion of the cladding layer at the top of the trench, and A silicon layer is formed over and adjacent to the insulating layer.
14. 14. The method of claim 13, wherein the forming of the first waveguide comprises: Depositing a cladding material to line the trench, and A core material is deposited on the cladding layer to fill the trench.
15. 15. The method of claim 13, wherein the forming of the first waveguide comprises: depositing a cladding material to fill the trench; recessing the cladding material to leave a lower cladding layer for the first waveguide at the bottom of the trench; Depositing a core material on the lower cladding layer to fill the trench; Patterning the core material in the trench to form the core layer of the first waveguide and separating the core layer and sidewalls of the trench, and An additional cladding material is deposited to fill the space between the core layer and the sidewalls of the trench and to form an upper cladding layer over the lower cladding layer.
16. 16. The method of claim 13, further comprising: simultaneously forming additional trenches in the substrate during the formation of the trenches, and The additional trench is filled with an insulating material to form an insulating region, wherein the insulating material of the insulating region and a cladding material for the first waveguide are the same material, and wherein the insulating layer is deposited on the substrate to cover both the first waveguide and the insulating region.
17. 17. The method of claim 13, further comprising: forming an insulating region in the silicon layer, and A second waveguide is formed over the insulating region, wherein a size of a core layer of the second waveguide is smaller than a size of the core layer of the first waveguide.
18. 18. The method of claim 17, further comprising forming a waveguide extension extending through the insulating region and the insulating layer, wherein the second waveguide is formed after the waveguide extension such that the core layer of the second waveguide contacts the waveguide extension.
19. 19. The method of claim 17, further comprising forming at least one of a third waveguide, an additional optical device, and an electronic device using the silicon layer.

Description

Silicon-on-insulator chip structure with substrate embedded optical waveguide and method Technical Field The present invention relates to Integrated Circuits (ICs), and more particularly, to embodiments of silicon-on-insulator (SOI) chip structures having at least one optical waveguide (optical waveguide), and embodiments of methods of forming SOI chip structures. Background An Integrated Circuit (IC) chip may incorporate a combination of both optical and electronic devices. Such a chip may be a bulk semiconductor (e.g., bulk silicon) chip structure or a semiconductor-on-insulator (e.g., silicon-on-insulator (SOI)) chip structure. Advantages associated with SOI chip structures include, but are not limited to, improved isolation, improved radiation tolerance, and reduced parasitic capacitance. One disadvantage associated with SOI chip structures involves integrating both optical and electronic devices into the same SOI chip structure. In particular, in SOI chip structures having both optical and electronic devices, the maximum size of the core layer of the optical waveguide may be limited by other critical dimensions (critical dimensions; CDs). Unfortunately, since the dimensions of the core layer of the optical waveguide determine the characteristics of the optical waveguide, including the cut-off wavelength (i.e., the maximum wavelength of any optical signal that can be propagated by the waveguide), any limitations on the dimensions of the core layer can also affect functionality. Disclosure of Invention Embodiments of a silicon-on-insulator (SOI) chip structure are disclosed. The structure may include a substrate. The trench may extend into the substrate from a top surface to a bottom surface of the substrate. The structure may also include a substrate-embedded optical waveguide (referred to herein as a first waveguide) within the trench. The first waveguide may include a cladding (cladding) layer lining the trench and a core layer on the cladding layer such that the bottom and sides of the core layer are clad by the cladding layer. The structure may further include an insulating layer on the top surface of the substrate and extending laterally over the first waveguide. The structure may also include a silicon layer on the insulating layer and one or more front-end-of-the-line (FEOL) devices having components in and/or above the silicon layer (i.e., above the insulating layer). FEOL devices may include, for example, additional optical devices and/or electronic devices. Also disclosed herein are embodiments of methods for forming the above-described SOI chip structures. Generally, the method may include providing a substrate. A trench may be formed in the substrate extending from the top surface to the bottom surface. A substrate-embedded optical waveguide (referred to herein as a first waveguide) may be formed in the trench such that it includes a cladding layer and a core layer. A cladding layer may line the bottom and sidewalls of the trench. The core layer may be located in a trench on the cladding layer such that its bottom and sides are clad by the cladding layer. An insulating layer may be formed on the top surface of the substrate such that it covers the first waveguide. After forming the insulating layer, a silicon layer may be formed on the insulating layer. After forming the silicon layer on the insulating layer, FEOL processes may be performed to form one or more FEOL devices (e.g., additional optical devices and/or electronic devices) having components in and/or over the silicon layer (i.e., over the insulating layer). Drawings The invention will be better understood from the following detailed description with reference to the drawings, which are not necessarily drawn to scale, in which: FIG. 1 is a cross-sectional view of a chip structure having optical and electronic device areas; FIGS. 2A-2B illustrate different cross-sectional views AA and BB, respectively, of an embodiment of a silicon-on-insulator (SOI) chip structure having a substrate embedded in an optical waveguide; Fig. 2C is a cross-sectional view AA and BB directions of fig. 2A to 2B (described above) and an exemplary layout of fig. 3A to 3B (described below); FIGS. 3A-3B are different cross-sectional views AA and BB, respectively, showing another embodiment of an SOI chip structure with a substrate embedded optical waveguide; FIG. 4 is a schematic cross-sectional view of another embodiment of an SOI chip structure with a substrate embedded in an optical waveguide; FIG. 5 is a flow chart of an embodiment of the disclosed method; FIGS. 6 and 7 are cross-sectional views of partially completed structures formed in accordance with the flow chart of FIG. 5; FIGS. 8-10 are cross-sectional views of a partially completed structure formed according to process flow A of the flow chart of FIG. 5, and FIGS. 11-21 are cross-sectional views of partially completed structures formed according to process flow B of the flow chart of FIG. 5; Descri