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CN-114691082-B - Multiplier circuit, chip, electronic device, and computer-readable storage medium

CN114691082BCN 114691082 BCN114691082 BCN 114691082BCN-114691082-B

Abstract

The disclosed embodiments disclose a multiplier circuit, a chip, an electronic device, and a computer-readable storage medium. The multiplier circuit comprises a calculation circuit, a data reading circuit, a format selection circuit and a storage circuit, wherein the format selection circuit is used for determining an operation mode according to a format selection signal, the operation mode indicates the format of input data, the data reading circuit is used for reading the input data corresponding to the operation mode from the storage circuit according to the operation mode, and the calculation circuit performs multiplication operation according to the operation mode and the input data to obtain a calculation result. The multiplier circuit determines the format of the input data through the format selection circuit, so that the calculation of the input data with various formats can be performed by using one multiplier circuit, and the technical problem of chip area waste in the prior art is solved.

Inventors

  • PAN WEIXING
  • FENG JIE

Assignees

  • 北京希姆计算科技有限公司

Dates

Publication Date
20260505
Application Date
20201231

Claims (9)

  1. 1. A multiplier circuit, comprising: a calculation circuit, a data reading circuit, a format selection circuit and a storage circuit; The format selection circuit is used for determining an operation mode according to the format selection signal, wherein the operation mode indicates the format of input data; the data reading circuit is used for reading input data corresponding to the operation mode from the storage circuit according to the operation mode; The computing circuit performs multiplication operation according to the operation mode and the input data to obtain a computing result; The data reading circuit comprises a switching circuit, wherein the switching circuit is used for determining the states of switches in the switching circuit according to the format of data indicated by the operation mode so as to read corresponding data from the storage circuit through the opened switches, and the opening quantity of different switches corresponds to the data in different formats.
  2. 2. The multiplier circuit of claim 1, wherein the data read circuit comprises: A first input data reading circuit for reading sign bits, exponent bits, and mantissa bits of first input data from the storage circuit according to the operation mode; and the second input data reading circuit is used for reading sign bits, exponent bits and mantissa bits of the second input data from the storage circuit according to the operation mode.
  3. 3. A multiplier circuit as claimed in claim 1 or 2, in which the data read circuit comprises: a sign reading circuit, an exponent reading circuit and a mantissa reading circuit, The symbol reading circuit is used for reading symbol bits of input data corresponding to the operation mode from the storage circuit according to the operation mode; The exponent reading circuit is used for reading exponent bits of input data corresponding to the operation mode from the storage circuit according to the operation mode; the mantissa reading circuit is used for reading mantissa bits of input data corresponding to the operation mode from the storage circuit according to the operation mode.
  4. 4. The multiplier circuit of claim 2, wherein the calculation circuit comprises: a sign bit calculation circuit, a multiplication circuit and an addition circuit, The sign bit calculating circuit is used for calculating sign bits of output data according to the sign bits of the first input data and the sign bits of the second input data; The multiplication circuit is used for calculating the tail bits of output data according to the operation mode, the tail bits of the first input data and the tail bits of the second input data and generating an exponent adjusting signal; The addition circuit is used for calculating the index value of output data according to the operation mode, the index value of the first input data, the index value of the second input data and the index adjustment signal.
  5. 5. The multiplier circuit of claim 4, wherein said multiplier circuit comprises: A base multiplication calculation circuit and a rounding normalization circuit, wherein, The basic multiplication circuit is used for carrying out multiplication on the mantissa bits of the first input data and the mantissa bits of the second input data according to the width of the mantissa of the input data corresponding to the operation mode to obtain initial mantissa bits of the output data; The rounding normalization circuit is used for normalizing and rounding the initial mantissa bit according to the width of the bit number of the input data to obtain the mantissa bit of the output data and the exponent adjusting signal.
  6. 6. A multiplier circuit as claimed in claim 4 or 5, wherein the adding circuit comprises: a basic addition calculation circuit and an exponent adjusting circuit, wherein, The basic addition calculation circuit is used for carrying out addition calculation on the exponent bits of the first input data and the exponent bits of the second input data according to the width of the exponent of the input data corresponding to the operation mode to obtain initial exponent bits of output data; The index adjusting circuit is used for adjusting the initial index bit according to the index adjusting signal to obtain the index bit of the output data.
  7. 7. A multiplier circuit as claimed in claim 4 or 5, characterized in that: the sign bit calculating circuit, the multiplying circuit and the adding circuit store sign bits, exponent bits and mantissa bits of output data into the storing circuit in order to obtain the output data.
  8. 8. The multiplier circuit of claim 1, wherein the width of the calculation circuit, the width of the data read circuit and the width of the memory circuit are maximum widths in the format of the operation mode indication input data.
  9. 9. A floating point number multiplication method for use in a multiplier circuit according to any one of claims 1 to 8, comprising: Acquiring an operation mode; acquiring first input data and second input data according to an input data format corresponding to the operation mode; and multiplying the first input data and the second input data according to the operation mode to obtain output data.

Description

Multiplier circuit, chip, electronic device, and computer-readable storage medium Technical Field The present disclosure relates to the field of multipliers, and more particularly, to a multiplier circuit, a chip, an electronic device, and a computer-readable storage medium. Background With the development of science and technology, human society is rapidly entering the intelligent era. The important characteristics of the intelligent age are that the variety of data obtained by people is more and more, the amount of obtained data is more and more, and the requirement on the speed of processing the data is higher and more. Chips are the cornerstone of task scheduling, which fundamentally determines people's ability to process data. From the application field, the chip mainly has two routes, namely a general chip route, such as CPU (Central Processing Unit), which can provide great flexibility but has lower effective calculation force when processing algorithms in specific fields, and a special chip route, such as TPU (Tensor Processing Unit), which can exert higher effective calculation force in specific fields but faces the flexible and changeable more general fields, and has poorer processing capability and even cannot be processed. Because of the large variety and huge number of data in the intelligent age, the chip is required to have extremely high flexibility, can process algorithms in different fields and in daily life and in a very strong processing capacity, and can rapidly process extremely large and rapidly growing data volume. In processor design, it is often necessary to design various floating-point multiplier circuits to meet floating-point operation requirements of different precision and data formats. For example, for scenes with higher precision requirements, a 32-bit floating point multiplier circuit needs to be designed to meet the precision of 32-bit floating point calculation, while for scenes with lower precision requirements, a 16-bit floating point multiplier circuit needs to be involved to meet the precision of 16-bit floating point calculation. Therefore, in the prior art, the conventional multiplier cannot realize multiplication with two kinds of precision by using the same multiplier, so that the two multipliers are designed separately, thereby bringing about waste of chip area and increase of cost. Disclosure of Invention This summary is provided to introduce a selection of concepts in a simplified form that are further described below in the detailed description. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter. In order to solve the technical problems of inflexible task scheduling and complicated control of a processing core in the prior art, the embodiment of the disclosure provides the following technical scheme: In a first aspect, embodiments of the present disclosure provide a multiplier circuit comprising: The data reading circuit is used for reading input data corresponding to the operation mode from the storage circuit according to the operation mode, and the calculation circuit performs multiplication operation according to the operation mode and the input data to obtain a calculation result. Further, the data reading circuit includes: A first input data reading circuit for reading sign bits, exponent bits, and mantissa bits of first input data from the storage circuit according to the operation mode; and the second input data reading circuit is used for reading sign bits, exponent bits and mantissa bits of the second input data from the storage circuit according to the operation mode. Further, the data reading circuit includes: And the switching circuit is used for determining the state of a switch in the switching circuit according to the format of the data indicated by the operation mode so as to read corresponding data from the storage circuit through the opened switch. Further, the data reading circuit includes: a sign reading circuit, an exponent reading circuit and a mantissa reading circuit, The symbol reading circuit is used for reading symbol bits of input data corresponding to the operation mode from the storage circuit according to the operation mode; The exponent reading circuit is used for reading exponent bits of input data corresponding to the operation mode from the storage circuit according to the operation mode; the mantissa reading circuit is used for reading mantissa bits of input data corresponding to the operation mode from the storage circuit according to the operation mode. Further, the computing circuit includes: a sign bit calculation circuit, a multiplication circuit and an addition circuit, The sign bit calculating circuit is used for calculating sign bits of output data according to the sign bits of the first input data and the sign bits of the second input data; The multiplication circuit is used for ca