CN-114695311-B - Semiconductor device and method for manufacturing the same

Abstract

A semiconductor device includes a conductive feature, a dielectric layer disposed over the conductive feature, and a contact feature extending through the dielectric layer. The contact feature has an upper portion and a lower portion. The upper portion is separated from the dielectric layer by a spacer layer. The lower portion is electrically coupled to the conductive feature and in contact with the dielectric layer.

Inventors

• YAN CUILING
• CHEN JIANHONG

Assignees

• 台湾积体电路制造股份有限公司

Dates

Publication Date

20260508

Application Date

20210623

Priority Date

20210304

Claims (20)

1. 1. A semiconductor device, comprising: a first conductive feature; A first dielectric layer disposed over the first conductive feature, and A first contact feature extending through the first dielectric layer, the first contact feature electrically coupled to the first conductive feature; Wherein an upper portion of the first contact feature is laterally separated from a first inner sidewall of the first dielectric layer by a second dielectric layer, and a lower portion of the first contact feature is in contact with the first inner sidewall of the first dielectric layer, Wherein the first contact feature comprises an intermediate boundary extending laterally from a lower edge of a sidewall of the upper portion to an upper edge of a sidewall of the lower portion.
2. 2. The device of claim 1, wherein the first conductive feature comprises a feature selected from the group consisting of a drain feature of a first transistor, a source feature of the first transistor, a gate feature of the first transistor, and a first interconnect feature extending laterally in a metallization layer.
3. 3. The component of claim 2, further comprising: a second conductive feature, and A second contact feature extending through the first dielectric layer, the second contact feature electrically coupled to the second conductive feature; Wherein an upper portion of the second contact feature is laterally separated from a second inner sidewall of the first dielectric layer by a third dielectric layer that is substantially similar to the second dielectric layer.
4. 4. The device of claim 3, wherein the second conductive feature comprises a feature selected from the group consisting of the drain feature of the first transistor, the source feature of the first transistor, the gate feature of the first transistor, a drain feature of a second transistor, a source feature of the second transistor, a gate feature of the second transistor, and a second interconnect feature extending laterally in the metallized layer.
5. 5. The device of claim 3, wherein each of the second dielectric layer and the third dielectric layer is characterized by a first etch rate that is different from a second etch rate of the first dielectric layer.
6. 6. The device of claim 1, wherein the second dielectric layer comprises a material selected from the group consisting of an oxide-based dielectric material, a nitride-based dielectric material, and a polysilicon material.
7. 7. The device of claim 1, wherein a first lateral width of the lower portion is substantially less than a sum of a second lateral width of the upper portion and a thickness of the second dielectric layer.
8. 8. The device of claim 1, wherein a first lateral width of the lower portion is equal to or less than a sum of a second lateral width of the upper portion and one or more thicknesses of the second dielectric layer.
9. 9. The component of claim 6, wherein the first contact feature further comprises a lateral boundary at an intersection of the upper portion and the lower portion.
10. 10. A semiconductor device, comprising: A conductive feature; A dielectric layer disposed over the conductive feature, and A contact feature extending through the dielectric layer; wherein the contact feature has an upper portion separated from the dielectric layer by a spacer layer and a lower portion electrically coupled to the conductive feature and in contact with the dielectric layer, Wherein the contact feature comprises an intermediate boundary extending laterally from a lower edge of a side wall of the upper portion to an upper edge of a side wall of the lower portion.
11. 11. The element of claim 10, wherein a first lateral width of the lower portion of the contact feature is equal to or less than a third of a sum of a second lateral width of the upper portion of the contact feature and a thickness of one or more of the spacer layers.
12. 12. The device of claim 10 wherein the spacer layer comprises a material selected from the group consisting of an oxide-based dielectric material, a nitride-based dielectric material, and a polysilicon material.
13. 13. The device of claim 10 wherein the conductive feature comprises a feature selected from the group consisting of a drain feature of a transistor, a source feature of the transistor, a gate feature of the transistor, and an interconnect feature extending laterally in a metallization layer.
14. 14. A method of fabricating a semiconductor device, comprising: the recess is arranged on an upper part of a first dielectric layer above a conductive feature; filling the upper portion of the recess with a second dielectric layer to form a hole embedded in the second dielectric layer, wherein a width of the recess is greater than a width of the hole; Etching the second dielectric layer and the first dielectric layer to form a contact hole exposing at least a portion of the conductive feature using the hole such that at least a lower portion of the contact hole is vertically aligned with the conductive feature, and The contact hole is filled with a conductive material to form a contact feature electrically coupled to the conductive feature.
15. 15. The method of claim 14, wherein filling the upper portion of the recess with a second dielectric layer to form a hole further comprises: a deposition rate of filling the second dielectric layer is adjusted to form a protrusion of the second dielectric layer, the protrusion including a first portion and a second portion extending laterally toward each other to surround the hole.
16. 16. The method of claim 14, wherein etching the second dielectric layer and the first dielectric layer to form a contact hole further comprises: A portion of the second dielectric layer and a portion of the first dielectric layer are etched, each of the portion of the second dielectric layer and the portion of the first dielectric layer being vertically aligned with the hole, thereby leaving a remaining portion of the second dielectric layer and extending along an inner sidewall of an upper portion of the contact hole.
17. 17. The method of claim 14, wherein etching the second dielectric layer and the first dielectric layer to form a contact hole further comprises: etching the second dielectric layer and the first dielectric layer to form an upper portion of the contact hole while leaving a residual portion of the second dielectric layer and extending along an inner sidewall of an upper portion of the contact hole, and The first dielectric layer is etched by forming the lower portion of the contact hole to expose the conductive feature.
18. 18. The method as recited in claim 14, further comprising: The first dielectric layer and the second dielectric layer are polished to form a substantially planar surface before etching the second dielectric layer and the first dielectric layer to form a contact hole.
19. 19. The method of claim 14, wherein a first lateral width of an upper portion of the recess is substantially greater than a second lateral width of the lower portion of the contact hole.
20. 20. The method of claim 14, wherein a first lateral width of an upper portion of the recess is equal to or greater than three times a second lateral width of the lower portion of the contact hole.

Description

Semiconductor device and method for manufacturing the same Technical Field The present disclosure relates to a semiconductor device, and more particularly, to a contact feature of a semiconductor device and a method for fabricating the semiconductor device. Background The semiconductor industry has made significant progress in pursuing higher element densities and lower costs. During the development of semiconductor devices, the functional density (e.g., the number of interconnected conductive features per unit area of a wafer) has generally increased, while the geometry has decreased. This process of downsizing is generally beneficial by improving production efficiency and reducing associated costs. However, the increased functional density increases the complexity of the semiconductor element, for example, by reducing the distance between adjacent conductive features. As the distance between adjacent conductive features decreases, it may be difficult to form contact features for each conductive feature. For example, the distance between contact features typically decreases as the distance between adjacent conductive features decreases, which may significantly increase the likelihood of shorting of the contact features. Thus, there is a need for improved contact characteristics and improved methods of formation thereof. Disclosure of Invention One aspect of the present disclosure provides a semiconductor device including a first conductive feature, a first dielectric layer disposed over the first conductive feature, and a first contact feature extending through the first dielectric layer and electrically coupled to the first conductive feature. Wherein an upper portion of the first contact feature is laterally separated from the first inner sidewall of the first dielectric layer by the second dielectric layer and a lower portion of the first contact feature is in contact with the first inner sidewall of the first dielectric layer. Another aspect of the present disclosure provides a semiconductor device including a conductive feature, a dielectric layer disposed over the conductive feature, and a contact feature extending through the dielectric layer, wherein the contact feature has an upper portion separated from the dielectric layer by a spacer layer and a lower portion electrically coupled to the conductive feature and in contact with the dielectric layer. Yet another aspect of the present disclosure provides a method of fabricating a semiconductor device, comprising providing a recess (recessing) in an upper portion of a first dielectric layer over a conductive feature, filling the upper portion of the recess with a second dielectric layer to form a hole embedded in the second dielectric layer, etching the second dielectric layer and the first dielectric layer to form a contact hole exposing at least a portion of the conductive feature using the hole to vertically align at least a lower portion of the contact hole with the conductive feature, and filling the contact hole with a conductive material to form a contact feature electrically coupled to the conductive feature. Drawings The aspects of the present disclosure will be better understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that as is standard in the industry, many features are not drawn to scale. In fact, the dimensions of many of the features may be arbitrarily scaled for clarity of discussion. FIG. 1 is a flow chart depicting an exemplary method for forming a semiconductor device according to some embodiments; FIGS. 2-7 are cross-sectional views of an exemplary semiconductor device during various stages of fabrication, as fabricated by the method of FIG. 1, in accordance with some embodiments; FIG. 8A illustrates an exemplary semiconductor device including one or more contact features, which is fabricated by the method of FIG. 1, according to some embodiments; FIG. 8B is a corresponding top view of the semiconductor device of FIG. 8A, according to some embodiments; FIG. 9A illustrates another exemplary semiconductor device including one or more contact features, which is fabricated by the method of FIG. 1, in accordance with some embodiments; FIG. 9B is a corresponding top view of the semiconductor device of FIG. 9A, according to some embodiments; FIG. 10A illustrates yet another exemplary semiconductor device including one or more contact features, which is fabricated by the method of FIG. 1, in accordance with some embodiments; FIG. 10B is a corresponding top view of the semiconductor device of FIG. 10A, according to some embodiments; FIG. 11A illustrates yet another exemplary semiconductor device including one or more contact features, which is fabricated by the method of FIG. 1, in accordance with some embodiments; FIG. 11B is a corresponding top view of the semiconductor device of FIG. 11A, according to some embodiments; FIG. 12 is an exemplary top view of contact