CN-114695357-B - Semiconductor device, preparation method thereof and storage device

CN114695357BCN 114695357 BCN114695357 BCN 114695357BCN-114695357-B

Abstract

The invention discloses a semiconductor device and a preparation method thereof, wherein a semiconductor substrate with a conductive structure is provided, a plug connected with the conductive structure is prepared above the conductive structure, an infiltration layer is formed on the surface of the semiconductor substrate with the plug, the infiltration layer is an intermetallic compound, the intermetallic compound contains metal wire elements, electromigration-resistant metal elements and metal elements playing a role in adhesion, an upper metal layer containing the metal wire elements is formed above the infiltration layer, and patterning treatment is carried out on the infiltration layer and the upper metal layer to obtain an interconnection line for connecting the conductive structure. The invention can form the infiltration layer and the upper metal layer with uniform thickness, thereby improving reliability such as electromigration, stress migration and the like and ensuring the quality of semiconductor products.

Inventors

Jin Xuanyong
Guo Tiaoyuan
XU KANGYUAN
GAO JIANFENG
BAI GUOBIN
YANG TAO
LI JUNFENG
WANG WENWU

Assignees

中国科学院微电子研究所
真芯(北京)半导体有限责任公司

Dates

Publication Date: 20260505
Application Date: 20201231

Claims (12)

1. A method of manufacturing a semiconductor device, comprising: Providing a semiconductor substrate, wherein a conductive structure is formed on the semiconductor substrate; Preparing a plug connected with the conductive structure above the conductive structure; Forming a wetting layer on the surface of the semiconductor substrate on which the plug is formed, wherein the wetting layer is an intermetallic compound, the intermetallic compound contains a metal wire element, an electromigration-resistant metal element and a metal element with an adhesion effect, the metal wire element in the intermetallic compound is related to a metal material for subsequently forming an upper metal layer, the electromigration-resistant metal element is Cu or other metal elements with the same or similar electron mobility as Cu, the metal element with the adhesion effect is any one metal element of Ti, ta and Ni, the metal wire element is aluminum or aluminum alloy, and the intermetallic compound is TiAlCu, taAlCu, crAlCu or NiAlCu; Forming an upper metal layer including the metal line element over the wetting layer; And carrying out graphical treatment on the wetting layer and the upper metal layer to obtain an interconnection line for connecting the conductive structure.
2. The method of claim 1, wherein the wetting layer has a thickness of less than 100nm.
3. The method of claim 1, wherein forming an upper metal layer comprising the metal line element over the wetting layer comprises: and forming the upper metal layer under the deposition condition of 350-500 ℃.
4. The method of claim 1, wherein forming an upper metal layer comprising the metal line element over the wetting layer comprises: Forming the upper metal layer at normal temperature; And annealing the deposited upper metal layer at 500-600 ℃.
5. The method of claim 1, further comprising, prior to said patterning said wetting layer and said upper metal layer: A capping layer is formed over the upper metal layer.
6. The method according to claim 5, wherein the cover layer is in particular: TiN layer, or A composite layer formed by TiN and Ti.
7. The method of claim 1, wherein preparing a plug connected to the conductive structure over the conductive structure comprises: Forming a contact hole above the conductive structure; And forming the plug in the contact hole.
8. The method of claim 7, wherein forming the plug within the contact hole comprises: Forming a barrier layer in the contact hole by utilizing a PVD (physical vapor deposition), CVD (chemical vapor deposition) or ALD (atomic layer deposition) process; the plugs are formed in the contact holes where the barrier layer is deposited using PVD, CVD, ALD or an electroplating process.
9. A semiconductor device, comprising: a semiconductor substrate; a conductive structure located above the semiconductor substrate; the plug is positioned above the conductive structure and connected with the conductive structure; The interconnection line comprises a patterned wetting layer and a patterned upper metal layer, wherein the wetting layer is positioned on the surface of a semiconductor substrate on which the plug is formed, the upper metal layer is positioned above the wetting layer, the wetting layer is an intermetallic compound, the intermetallic compound contains a metal wire element, an electromigration-resistant metal element and a bonding metal element, the metal wire element in the intermetallic compound is related to a metal material for subsequently forming the upper metal layer, the electromigration-resistant metal element is Cu or other metal elements with the same or similar electron mobility as Cu, the bonding metal element is any one metal element of Ti, ta and Ni, the metal wire element is aluminum or aluminum alloy, and the intermetallic compound is TiAlCu, taAlCu, crAlCu or NiAlCu.
10. The semiconductor device of claim 9, wherein the metal line element is Al or an aluminum alloy.
11. The semiconductor device of claim 10, wherein the intermetallic compound is TiAlCu, taAlCu, crAlCu or NiAlCu.
12. A memory device comprising the semiconductor device of any one of claims 9-11.

Description

Semiconductor device, preparation method thereof and storage device Technical Field The invention belongs to the field of semiconductors, and particularly relates to a semiconductor device manufacturing method, a semiconductor device and a memory device. Background There are various metallization structures depending on the type of semiconductor device and the fabrication process. The metallization structure of the memory device, (e.g., DRAM), al or Cu is used as a connection for power lines, requiring a tight control of the process window of each process. Generally, the metallization of Al is composed of a wetting layer (WETTING LAYER), al or an aluminum alloy, and a capping layer. In the metallization structure of Al, a Ti film is generally used for the wetting layer in consideration of the dielectric properties and adhesion of the oxide. In the subsequent grain growth process of the Al element, a TiAlx compound is generated due to a reaction between the Ti element and the Al element of the wetting layer, which is difficult to control, and thus causes high resistance and uneven thickness of the metallization structure. In order to solve these problems, the conventional technique is to cope with the problem of lowering the temperature of grain growth, which results in deterioration of reliability problems such as electromigration and stress migration. Disclosure of Invention Aiming at the problems existing in the prior art, the embodiment of the invention provides a semiconductor device, a preparation method thereof and a storage device, so as to form an infiltration layer and an upper metal layer with uniform thickness of the semiconductor device, thereby optimizing the reliability problems of the semiconductor device in aspects of electromigration, stress migration and the like. In a first aspect, an embodiment of the present invention provides a method for manufacturing a semiconductor device, including: Providing a semiconductor substrate, wherein a conductive structure is formed on the semiconductor substrate; Preparing a plug connected with the conductive structure above the conductive structure; Forming a wetting layer on the surface of the semiconductor substrate on which the plug is formed, wherein the wetting layer is an intermetallic compound, and the intermetallic compound contains a metal wire element, an electromigration-resistant metal element and a metal element with an adhesion function; Forming an upper metal layer including the metal line element over the wetting layer; And carrying out graphical treatment on the wetting layer and the upper metal layer to obtain an interconnection line for connecting the conductive structure. Optionally, the metal wire element is aluminum or an aluminum alloy. Optionally, the intermetallic compound is TiAlCu, taAlCu, crAlCu or NiAlCu. Optionally, the thickness of the wetting layer is below 100nm. Optionally, forming an upper metal layer including the metal line element above the wetting layer includes: and forming the upper metal layer under the deposition condition of 350-500 ℃. Optionally, forming an upper metal layer including the metal line element above the wetting layer includes: Forming the upper metal layer at normal temperature; And annealing the deposited upper metal layer at 500-600 ℃. Optionally, before the patterning the wetting layer and the upper metal layer, the method further includes: A capping layer is formed over the upper metal layer. Optionally, the covering layer specifically includes: TiN layer, or A composite layer formed by TiN and Ti. Optionally, preparing a plug connected with the conductive structure above the conductive structure, including: Forming a contact hole above the conductive structure; And forming the plug in the contact hole. Optionally, forming the plug in the contact hole includes: Forming a barrier layer in the contact hole by utilizing a PVD (physical vapor deposition), CVD (chemical vapor deposition) or ALD (atomic layer deposition) process; the plugs are formed in the contact holes where the barrier layer is deposited using PVD, CVD, ALD or an electroplating process. In a second aspect, an embodiment of the present invention provides a semiconductor device including: a semiconductor substrate; a conductive structure located above the semiconductor substrate; the plug is positioned above the conductive structure and connected with the conductive structure; The interconnection line comprises a patterned wetting layer and a patterned upper metal layer, wherein the wetting layer is positioned on the surface of the semiconductor substrate on which the plug is formed, the upper metal layer is positioned above the wetting layer, the wetting layer is an intermetallic compound, and the intermetallic compound contains metal wire elements, electromigration-resistant metal elements and metal elements with an adhesion effect. Optionally, the metal wire element is Al or an aluminum alloy. Optionally, the intermetallic com