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CN-114696638-B - Centralized control type staggered parallel circuit, current equalizing method thereof and readable storage medium

CN114696638BCN 114696638 BCN114696638 BCN 114696638BCN-114696638-B

Abstract

The invention relates to a current equalizing method of a centralized control type staggered parallel circuit, which comprises the steps of setting the duty ratio of a first parallel circuit in the staggered parallel circuit as a first duty ratio, setting the duty ratio of a second parallel circuit in the staggered parallel circuit as a second duty ratio, and setting a second duty ratio compensation amount for ensuring that the currents of two parallel circuits are equal when one switching cycle is finished based on the first duty ratio and the ratio between the voltage difference value of the input voltage sampled by the zero crossing point of a triangular carrier of the first parallel circuit and the input voltage sampled by a period value and the bus voltage value of the staggered parallel circuit. The invention also relates to a computer readable storage medium and a centralized control type staggered parallel circuit. The invention can solve the problem of non-current sharing among circuits in a low-cost and easy-to-implement mode and improve the sine degree of the second parallel circuit.

Inventors

  • SONG QIONG

Assignees

  • 维谛公司

Dates

Publication Date
20260508
Application Date
20201231

Claims (8)

  1. 1. A current sharing method for a centralized control type staggered parallel circuit, comprising the steps of: s1, setting the duty ratio of a first parallel circuit in the staggered parallel circuit as a first duty ratio, and setting the duty ratio of a second parallel circuit in the staggered parallel circuit as a second duty ratio; S2, setting a ratio between a voltage difference value of an input voltage sampled based on a zero crossing point of a triangular carrier of the first parallel circuit and an input voltage sampled based on a period value and a bus voltage value of the staggered parallel circuit to a second duty cycle compensation amount which ensures that currents of the two parallel circuits are equal when one switching period is finished, and calculating the second duty cycle based on a difference between the first duty cycle and the second duty cycle compensation amount; S3, calculating the real-time current of a second parallel circuit in the staggered parallel circuit based on the real-time current of the first parallel circuit, the first duty cycle and the compensation quantity of the second duty cycle, and performing closed-loop control on the second parallel circuit based on the real-time current of the second parallel circuit; in the step S2 of the process described above, Wherein Representing the second duty cycle of the signal to be applied, Representing the first duty cycle of the signal to be applied, Representing the second amount of duty cycle compensation, Representing the bus voltage value of the interleaved parallel circuit, Representing a switching period of the interleaved parallel circuit; Indicating that the input voltage is at Time of day and [ ] ) A difference in time; representing the input voltage of the zero crossing samples of the triangular carrier of the first parallel circuit.
  2. 2. The current equalizing method of a centralized control type interleaved parallel circuit according to claim 1 wherein in the step S3, the midpoint current of the second parallel circuit in the rising phase of the nth switching period is calculated based on the following formula: Wherein, the A midpoint current representing a rising phase of the second parallel circuit, A midpoint current representing a rising phase of the first parallel circuit, Representing the inductance value of the first parallel circuit or the second parallel circuit, The number of cycles is represented and the value is a positive integer, Representing the input voltage of the interleaved parallel circuit.
  3. 3. The current sharing method of the centralized control type interleaved parallel circuit according to claim 2 wherein in the step S3, the midpoint current of the second parallel circuit in the falling phase in the nth switching period is calculated based on the following formula: Wherein, the A midpoint current representing a falling phase of the second parallel circuit, Representing the midpoint current of the falling phase of the first parallel circuit.
  4. 4. The current equalizing method of a centralized control type staggered parallel circuit according to claim 3, wherein the real-time current of the first parallel circuit and the real-time current of the second parallel circuit are equal at the beginning time of any switching period and are also equal at the ending time of any switching period but are not equal at the ending time of energy storage; In the time-course of which the first and second contact surfaces, The current ripple of the second parallel circuit is larger than the current ripple of the first parallel circuit; In the time-course of which the first and second contact surfaces, The current ripple of the second parallel circuit is smaller than the current ripple of the first parallel circuit.
  5. 5. The method of current sharing in a centralized control type interleaved parallel circuit according to claim 4 wherein the interleaved parallel circuit comprises PFC interleaved parallel circuit and INV interleaved parallel circuit.
  6. 6. The current sharing method of a centralized control type interleaved parallel circuit according to claim 4 wherein the interleaved parallel circuit comprises N parallel circuits, wherein N is a positive integer greater than or equal to 2.
  7. 7. A computer readable storage medium, on which a computer program is stored, characterized in that the computer program, when being executed by a processor, implements a method for current sharing of a centrally controlled interleaved parallel circuit according to any of claims 1-6.
  8. 8. A centralized control type staggered parallel circuit comprising at least a first parallel circuit, a second parallel circuit and a controller, wherein a computer program is stored on the controller, and is characterized in that the computer program, when executed by the controller, realizes the current sharing method of the centralized control type staggered parallel circuit according to any one of claims 1-6.

Description

Centralized control type staggered parallel circuit, current equalizing method thereof and readable storage medium Technical Field The present invention relates to the field of interleaved parallel circuits, and more particularly, to a current equalizing method for a centralized control type interleaved parallel circuit, a computer readable storage medium, and a centralized control type interleaved parallel circuit. Background Compared with a low-power circuit, the EMI circuit and the energy storage filtering parameter of the high-power circuit are correspondingly increased, and the requirement on the current stress of the switch tube is relatively larger. In order to realize miniaturization and light weight of products, a staggered parallel technology is introduced. The staggered parallel connection can reduce inductance current ripple and switch tube current stress, reduce circuit parameters and improve power density. The staggered parallel control can be realized by a centralized or decentralized control method. Decentralized can improve system reliability, but control is relatively complex and costly, so centralized control is commonly employed in the prior art. But the centralized staggered parallel circuit has the problem of non-current sharing among multiple paths. Disclosure of Invention The invention aims to solve the technical problems by providing a current equalizing method of a centralized control type staggered parallel circuit, a computer-readable storage medium and the centralized control type staggered parallel circuit aiming at the defects of the prior art, and the problem of non-current equalizing among circuits can be solved in a low-cost and easy-to-realize mode. The invention solves the technical problems by adopting the technical scheme that the current equalizing method for the centralized control type staggered parallel circuit is constructed and comprises the following steps: s1, setting the duty ratio of a first parallel circuit in the staggered parallel circuit as a first duty ratio, and setting the duty ratio of a second parallel circuit in the staggered parallel circuit as a second duty ratio; s2, setting a ratio between a voltage difference value of an input voltage sampled based on the first duty ratio and a zero crossing point of a triangular carrier of the first parallel circuit and an input voltage sampled based on a period value and a bus voltage value of the staggered parallel circuit as a second duty ratio compensation amount for ensuring equal currents of the two parallel circuits when one switching period is finished. The current equalizing method of the centralized control type staggered parallel circuit of the invention further comprises the following steps: And S3, calculating the real-time current of a second parallel circuit in the staggered parallel circuit based on the real-time current of the first parallel circuit, the first duty cycle and the compensation quantity of the second duty cycle, and performing closed-loop control on the second parallel circuit based on the real-time current of the second parallel circuit. In the current equalizing method of the centralized control type staggered parallel circuit of the invention, in the step S2,WhereinRepresenting the second duty cycle of the signal to be applied,Representing the first duty cycle of the signal to be applied,Representing the amount of compensation for the second duty cycle,Representing the bus voltage value of the interleaved parallel circuit,Representing the switching period of the interleaved parallel circuit. In the current equalizing method of the centralized control type staggered parallel circuit, the first parallel circuit and the second parallel circuit are the same circuit, and in the step S3, the midpoint current of the second parallel circuit in the rising stage in the nth switching period is calculated based on the following formula: Wherein, the A midpoint current representing a rising phase of the second parallel circuit,A midpoint current representing a rising phase of the first parallel circuit,Representing the inductance value of the first parallel circuit or the second parallel circuit,The number of cycles is represented and the value is a positive integer,Representing the input voltage of the interleaved parallel circuit,Indicating that the input voltage is atTime of day and [ ])Time difference. In the current equalizing method of the centralized control type staggered parallel circuit, in the step S3, the midpoint current of the second parallel circuit in the falling stage in the nth switching period is calculated based on the following formula: Wherein, the A midpoint current representing a falling phase of the second parallel circuit,Representing the midpoint current of the falling phase of the first parallel circuit. In the current equalizing method of the centralized control type staggered parallel circuit, the real-time current of the first parallel circuit and the real-t