CN-114724616-B - Parity data in Dynamic Random Access Memory (DRAM)

Abstract

The present disclosure describes methods, apparatus, and systems related to storing parity data in dynamic random access memory, DRAM. In an example, a method may include generating parity data at a controller based on user data queued for writing to a non-volatile memory device, receiving the parity data at a DRAM device from the controller and writing the parity data to the DRAM device, receiving the user data at a non-volatile memory device from the controller and writing the user data to the non-volatile memory device, reading the user data from the non-volatile memory device via the controller, and receiving the parity data at the controller from the DRAM device.

Inventors

• S. K. mirawarrap
• T. A. Marquardt

Assignees

• 美光科技公司

Dates

Publication Date

20260512

Application Date

20211220

Priority Date

20201222

Claims (19)

1. 1. A method for managing parity data (226) in a dynamic random access memory, DRAM, (222), comprising: Generating, at a controller (114, 214), parity data based on user data (224) queued for writing to a non-volatile memory device (220) coupled to the controller; receiving the parity data from the controller at the DRAM and writing the parity data to the DRAM; receiving the user data from the controller at the non-volatile memory device and writing the user data to the non-volatile memory device; Reading the user data from the non-volatile memory device via the controller; receiving the parity data from the DRAM at the controller, and The user data is reconstructed at the controller in one clock cycle.
2. 2. The method of claim 1, further generating the parity data at the controller by performing an error correction code, ECC, operation on the user data using an error correction code, ECC, module (118, 218).
3. 3. The method of claim 1, further comprising writing the parity data to the non-volatile memory device.
4. 4. The method of claim 3, wherein a bitstream comprising the user data further comprises one or more bits of the parity data.
5. 5. The method of claim 1, further comprising reconstructing, at the controller, the user data using the parity data in response to receiving the parity data at the controller.
6. 6. The method of claim 1, further comprising storing the parity data in the non-volatile memory device prior to powering down the DRAM.
7. 7. The method of claim 6, further comprising rewriting the parity data to the DRAM in response to powering on the DRAM.
8. 8. The method of claim 1, further comprising regenerating the parity data at the controller in response to powering down and powering up the DRAM.
9. 9. An apparatus for managing parity data (226) in a dynamic random access memory, DRAM, (222), comprising: the DRAM is configured to store the parity data; A non-volatile memory device (220) coupled to the DRAM, wherein the non-volatile memory device is configured to store user data (224), and A controller (114, 214) coupled to the DRAM and the non-volatile memory device, wherein the controller includes an error correction code, ECC, module (118, 218) configured to: Receiving the parity data from the DRAM; reconstructing the user data using the parity data in response to an error during a read operation of the user data from the non-volatile memory device, and The parity data is regenerated in response to powering down the DRAM.
10. 10. The apparatus of claim 9, wherein the ECC module is configured to generate the parity data.
11. 11. The apparatus of claim 10, wherein the ECC module is configured to perform an XOR operation on the user data to generate the parity data.
12. 12. The apparatus of claim 10, wherein the DRAM is configured to receive the parity data in response to the ECC module generating the parity data.
13. 13. The apparatus of claim 9, wherein the non-volatile memory device is a 3D cross-point device.
14. 14. The apparatus of claim 9, wherein the non-volatile memory device is a NAND device.
15. 15. A system for managing parity data (226) in a dynamic random access memory, DRAM, (222), comprising: A host device (102) configured to send a write command including user data (224), and A memory device (210) coupled to the host device, wherein the memory device comprises: A controller (114, 214) including an error correction code, ECC, module (118, 218) configured to: Receiving the write command including the user data, and Generating the parity data based on the user data; The DRAM configured to: receiving the parity data from the controller, and Storing the parity data A non-volatile memory device (220) configured to: Receiving the user data from the controller; Storing the user data The parity data is stored prior to powering down the DRAM.
16. 16. The system of claim 15, wherein the memory device is a nonvolatile dual inline memory module, NVDIMM.
17. 17. The system of claim 15, wherein the non-volatile memory device is configured to transmit the user data to the controller in response to receiving a read command from the host device.
18. 18. The system of claim 15, wherein the controller is configured to receive the parity data from the DRAM.
19. 19. The system of claim 18, wherein the ECC module is configured to reconstruct the user data using the parity data and send the user data to the host device in response to an error during a read operation of the user data from the non-volatile memory device.

Description

Parity data in Dynamic Random Access Memory (DRAM) Technical Field The present disclosure relates generally to managing parity data in Dynamic Random Access Memory (DRAM). Background Memory devices are typically provided as internal semiconductor integrated circuits in computers or other electronic devices. There are many different types of memory, including volatile and non-volatile memory. Volatile memory may require power to maintain its data and includes Random Access Memory (RAM), DRAM, synchronous Dynamic Random Access Memory (SDRAM), and the like. Nonvolatile memory can provide persistent data by preserving stored data when not powered and can include NAND flash memory, NOR flash memory, read-only memory (ROM), electrically Erasable Programmable ROM (EEPROM), erasable Programmable ROM (EPROM), and resistance variable memory, such as Phase Change Random Access Memory (PCRAM), resistive Random Access Memory (RRAM), magnetoresistive Random Access Memory (MRAM), and the like. Memory is also used as volatile and non-volatile data storage for a wide range of electronic applications. Nonvolatile memory may be used in, for example, personal computers, portable memory sticks, digital cameras, cellular telephones, portable music players such as MP3 players, movie players, and other electronic devices. The memory cells may be arranged in an array, where the array is used in a memory device. The memory may be part of a memory module used in the computing device, such as a dual in-line memory module (DIMM). The memory module may include volatile memory (e.g., such as DRAM) and/or non-volatile memory (e.g., such as flash memory or RRAM). DIMMs may be used as main memory in computing systems. Disclosure of Invention In one aspect, this disclosure provides a method for managing parity data in a Dynamic Random Access Memory (DRAM) comprising generating, at a controller, the parity data based on user data queued for writing to a non-volatile memory device coupled to the controller, receiving, at the DRAM, the parity data from the controller and writing the parity data to the DRAM, receiving, at the non-volatile memory device, the user data from the controller and writing the user data to the non-volatile memory device, reading, via the controller, the user data from the non-volatile memory device, and receiving, at the controller, the parity data from the DRAM. In another aspect, the present disclosure further provides an apparatus for managing parity data in a Dynamic Random Access Memory (DRAM), comprising the DRAM configured to store the parity data, a non-volatile memory device coupled to the DRAM, wherein the non-volatile memory device is configured to store user data, and a controller coupled to the DRAM and the non-volatile memory device, wherein the controller includes an Error Correction Code (ECC) module configured to receive the parity data from the DRAM, and reconstruct the user data using the parity data in response to an error during a read operation of the user data from the non-volatile memory device. In yet another aspect, this disclosure further provides a system for managing parity data in a Dynamic Random Access Memory (DRAM) comprising a host device configured to send a write command including user data, and a memory device coupled to the host device, wherein the memory device comprises a controller configured to receive the write command including the user data and generate the parity data based on the user data, the DRAM configured to receive the parity data from the controller and store the parity data, and a nonvolatile memory device configured to receive the user data from the controller and store the user data. Drawings Fig. 1 is a block diagram of an apparatus in the form of a computing system including a memory system in accordance with several embodiments of the present disclosure. Fig. 2 is a block diagram of a device in the form of a dual in-line memory module (DIMM) in accordance with several embodiments of the present disclosure. FIG. 3 is a flow chart of a method for storing parity data in a DRAM according to several embodiments of the present disclosure. Detailed Description The disclosure includes methods, apparatus, and systems related to generating parity data at a controller based on user data queued for writing to a non-volatile memory device coupled to the controller, receiving the parity data from the controller and writing the parity data to the DRAM device at the DRAM device, receiving the user data from the controller and writing the user data to the non-volatile memory device at the non-volatile memory device, reading the user data from the non-volatile memory device via the controller, and receiving the parity data from the DRAM device at the controller. Nonvolatile memory devices and/or DRAMs may be included in DIMMs. The DIMM may be a non-volatile dual inline memory module (NVDIMM). In a number of embodiments, the non-volatile memory device may be a 3D cross point devi