CN-114730596-B - QLC programming method using fine data classification

Abstract

The present disclosure relates generally to improved fuzzy-fine programming. Data may be written to SLC memory. The data may then be decoded and then blurred and fine written to the MLC. After decoding, the data may be stored in a DRAM located at the front end or in an SRAM located in the flash manager before it is written to the MLC. After being stored in DRAM or SRAM, the data is then decoded and written to MLC.

Inventors

• S.A. gorobets
• A.D. Bennett
• Hiepe T.H.
• Ryan R. Jones

Assignees

• 闪迪技术公司
• 西部数据技术公司

Dates

Publication Date

20260421

Application Date

20201221

Priority Date

20200611

Claims (20)

1. 1. A data storage device, the data storage device comprising: one or more memory devices including SLC memory and MLC memory, and A controller coupled to the one or more memory devices, the controller configured to: Writing data to the SLC memory; writing the data obfuscation to an MLC memory, wherein writing the data obfuscation to the MLC memory comprises: retrieving the data from the SLC memory; decoding the data retrieved from the SLC memory; Encoding decoded data retrieved from the SLC memory, and Writing encoded data to the MLC memory, and The data is finely written to the MLC memory.
2. 2. A data storage device, the data storage device comprising: one or more memory devices including SLC memory and MLC memory, and A controller coupled to the one or more memory devices, the controller configured to: Writing data to the SLC memory; writing the data obfuscation to an MLC memory, wherein writing the data obfuscation to the MLC memory comprises: Retrieving the data from latches in the one or more memory devices; Decoding the data retrieved from the latch; encoding the decoded data retrieved from the latch, and Writing encoded data to the MLC memory, and Finely writing the data to the MLC memory, wherein the finely writing comprises: Decoding the data retrieved from the latch; Generating XOR data for the decoded data retrieved from the latch; transmitting the decoded data and the generated XOR data retrieved from the latch to a DRAM; encoding the transmitted data, and Encoded data is written to the MLC memory.
3. 3. The data storage device of claim 2, wherein decoding the data retrieved from a latch for fine writing is the same as decoding the data retrieved from a latch for the fuzzy writing.
4. 4. A data storage device, the data storage device comprising: one or more memory devices including SLC memory and MLC memory, and A controller coupled to the one or more memory devices, the controller configured to: Writing data to the SLC memory; writing the data obfuscation to an MLC memory, wherein writing the data obfuscation to the MLC memory comprises: Retrieving the data from latches in the one or more memory devices; Decoding the data retrieved from the latch; encoding the decoded data retrieved from the latch, and Writing encoded data to the MLC memory; Finely writing the data into the MLC memory, and Performing garbage collection, wherein the garbage collection comprises: Reading data from the MLC memory; Decoding the read data; generating XOR data for the read data; Encoding the generated XOR data and the read data, and Encoded data is written to the MLC memory in a fuzzy manner.
5. 5. The data storage device of claim 4, wherein the garbage collection further comprises a fine write of data to MLC memory, wherein the fine write comprises: Decoding the data read from the MLC; Generating XOR data for the read data; transmitting the read data and the generated XOR data to a DRAM; encoding the transmitted data, and Encoded data is finely written to the MLC memory.
6. 6. The data storage device of claim 5, wherein decoding the data retrieved from a latch for fine writing is the same as decoding the data retrieved from a latch for the fuzzy writing.
7. 7. A data storage device, the data storage device comprising: one or more memory devices including SLC memory and MLC memory, and A controller coupled to the one or more memory devices, the controller configured to: Writing data to the SLC memory; writing the data obfuscation to an MLC memory, wherein writing the data obfuscation to the MLC memory comprises: Retrieving the data from latches in the one or more memory devices; Decoding the data retrieved from the latch; Generating XOR data for the decoded data retrieved from the latch; Transmitting the generated XOR data to the DRAM; encoding the decoded data retrieved from the latch, and Writing encoded data to the MLC memory, and The data is finely written to the MLC memory.
8. 8. A data storage device, the data storage device comprising: one or more memory devices each comprising a plurality of dies, wherein each die comprises SLC memory and MLC memory, and A controller coupled to the one or more memory devices, the controller configured to: Writing data to SLC memory; reading data from SLC memory; Decoding the read data; Transmitting the decoded data to the DRAM; First encoding the transmitted data, and The first encoded data is first written to the MLC memory.
9. 9. The data storage device of claim 8, wherein the controller is further configured to encode the transmitted data a second time.
10. 10. The data storage device of claim 9, wherein the controller is further configured to write second encoded data to the MLC memory.
11. 11. The data storage device of claim 10, wherein the first time encoded data is written to MLC memory a first time is a fuzzy write.
12. 12. The data storage device of claim 11, wherein writing the second encoded data a second time to MLC memory is a fine write.
13. 13. A data storage device, the data storage device comprising: one or more memory devices each comprising a plurality of dies, wherein each die comprises SLC memory and MLC memory, and A controller coupled to the one or more memory devices, the controller configured to: Writing data to SLC memory; reading data from SLC memory; Decoding the read data; Transmitting the decoded data to the DRAM; transmitting the decoded data to SRAM before transmitting the decoded data to DRAM; First encoding the transmitted data, and The first encoded data is first written to the MLC memory.
14. 14. The data storage device of claim 13, wherein the controller is further configured to encode some of the data transferred to the SRAM without transferring the data transferred to the SRAM to the DRAM.
15. 15. A data storage device, the data storage device comprising: One or more memory devices, wherein the one or more memory devices each comprise SLC memory and MLC memory; A controller coupled to the one or more memory devices, the controller configured to: Writing data to the SLC memory; reading the data from the SLC memory; Decoding the read data; delivering the decoded data to a first SRAM located in the front-end module; delivering the decoded data to a second SRAM located in a flash manager; Writing data transferred to the first SRAM in the MLC memory, and Writing data transferred to the second SRAM in the MLC memory.
16. 16. The data storage device of claim 15, wherein the controller is further configured to deliver the decoded data to a DRAM.
17. 17. The data storage device of claim 16, wherein the controller is further configured to encode the decoded data delivered to DRAM and write the encoded data to the MLC memory.
18. 18. The data storage apparatus of claim 17, wherein the encoded data written to the MLC memory is fine written.
19. 19. The data storage device of claim 15, wherein the data written from the first SRAM into the MLC memory is written vague.
20. 20. The data storage device of claim 15, wherein the data written from the second SRAM into the MLC memory is written vague.

Description

QLC programming method using fine data classification Cross Reference to Related Applications The present application claims priority from U.S. patent application Ser. No. 16/899,374, filed on 6/11 of 2020, which is incorporated herein by reference in its entirety. Background Technical Field Embodiments of the present disclosure generally relate to improving fuzzy-fine writing to QLCs. Description of related Art Programming or writing data may require two write phases, blurring and refinement. In fuzzy-fine programming, the bits to be written cannot be written only once. Instead, the data needs to be written first by fuzzy programming in which a voltage pulse is provided to push the current state to a higher resolution state, but not a fully resolved state. The fine programming is performed at a point of time after the fuzzy programming to write data again in a fully resolved state. In fuzzy-fine programming, for a biplane device, there are four page transfers for fuzzy programming and four page transfers for fine programming for a total of 128KB transfers for f. The vague state is unreadable and the data needs to be protected against possible power loss events (PLI). In addition, fuzzy-fine programming occurs in an interleaved word line sequence, which means that the data in transmission is five or eight times that of 128KB programmable cells. To perform fuzzy-fine programming, multiple megabytes may be programmed multiple times. In order to perform the multiple programming, a large amount of data needs to be set aside in order to perform the repeated programming with exactly the same data. Thus, there is a need in the art for improved fuzzy-fine programming. Disclosure of Invention The present disclosure relates generally to improved fuzzy-fine programming. Data may be written to SLC memory. The data may then be decoded and then blurred and fine written to the MLC. After decoding, the data may be stored in a DRAM located at the front end or in an SRAM located in the flash manager before it is written to the MLC. After being stored in DRAM or SRAM, the data is then decoded and written to MLC. In one embodiment, a data storage device includes one or more memory devices including SLC memory and MLC memory, and a controller coupled to the one or more memory devices, the controller configured to write data to the SLC memory, to blur write data to the MLC memory, wherein blurring write data to the MLC memory includes retrieving data from a latch in the one or more memory devices, decoding the data retrieved from the latch, encoding the decoded data retrieved from the latch, and writing the encoded data to the MLC memory, and fine writing the data to the MLC memory. In another embodiment, a data storage device includes one or more memory devices each including a plurality of dies, wherein each die includes SLC memory and MLC memory, and a controller coupled to the one or more memory devices, the controller configured to write data to the SLC memory, read data from the SLC memory, decode the read data, transmit the decoded data to a DRAM, first encode the transmitted data, and first write the first encoded data to the MLC memory. In another embodiment, a data storage device includes one or more memory devices, each having a plurality of dies, wherein the one or more memory devices each include SLC memory and MLC memory, and a controller coupled to the one or more memory devices, the controller configured to write data to the SLC memory, read data from the SLC memory, decode the read data, deliver the decoded data to a first SRAM located in a front-end module, deliver the decoded data to a second SRAM located in a flash manager, write data delivered to the first SRAM in the MLC memory, and write data delivered to the second SRAM in the MLC memory. Drawings So that the manner in which the above recited features of the present disclosure can be understood in detail, a more particular description of the disclosure, a brief summary of the disclosure, a more particular description of the disclosure, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this disclosure and are therefore not to be considered limiting of its scope, for the disclosure may admit to other equally effective embodiments. FIG. 1 is a schematic diagram of a system for storing data according to one embodiment. Fig. 2A and 2B are schematic diagrams of scheduling fuzzy-fine programming, according to various embodiments. Fig. 3 is a chart showing interleaved fuzzy-fine programming. Fig. 4A and 4B are schematic diagrams of scheduling fuzzy-fine programming and garbage collection, according to an embodiment. Fig. 5 is a schematic diagram of scheduling fuzzy-fine programming according to another embodiment. Fig. 6 is a schematic diagram of scheduling fuzzy-fine programming according to another